Sharp ER-A450T - Page 14

2) Block diagram
Fig. 2-4
MTD
MTD
RJMTR
SLMTD
SLMTS
SLMTR
SLMTD
TXDI
SCKI
RXDI
HTS1
SCK1
STH1
HTS2
SCK2
STH2
ROS1
ROS2
RAS1
RAS2
RAS3
OPTCS
AS
RD
WR
RDO
WRO
Φ
RESET
RES
VRESC
POFF
MD0
MD1
WAIT
RJRST
SLRST
*PRST
RJTMG
SLTMG
PTMG
INT4
INT1
INT2
INT3
EXINT0
EXINT1
EXINT2
EXINT3
SDT1~7 DT1~9
TEST
IRQ0
A23~A0
SSPRQ
SLF SLRS
VF
RF JF FCUT PCUT STAMP
TRGI
TRG TRG DOTEN
IRLON
D0~D7
Φ
Address decode
External CS
Internal CS
RASEL
Image
control
SSP comparison register
BAR.
Buffer
Read/write
control
Divider
CHS
serial select
Multiplexer
WAIT
control
CAPS
select
Print gate
Print pulse control
Print mode PMD
INTO
control
Printer control port
Motor
drive
* Output selection with CAPS.
PRST/PTMG.
EXWAIT
I/R Control
IRTX
IRRX
RCI
ASKRX
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