6. SSP circuit
1) Block diagram
This is the circuit employed for implementing the Special Service
Preset(SSP).
(Block diagram)
Fig. 6-1
(MPCA7 block diagram)
Fig. 6-2
As the address detection system, the break address register compari-
son system is employed though the mapping system and employed in
the conventional monitor RAM. The address register located in MPCA
is always compared with the system address bus to monitor and
generate the NMI signal at a synchronized timing and to go to the
NMI exception process.
In the exception process routine of the service routine, the entry
address is checked to go to the SSP sub routine.
Entry to the break address register (BAR) is performed through the
address FFFF00H or later decoded in MPCA7.
2) SSP register
The break address register (BAR) is accessed through the direct
address of FFFF00H~FFFFFFH. Entry number is 32 entry.
Fig. 6-3
Each BAR is composed of 4 a byte address. The bit composition is as
follows:
Fig. 6-4
is the enable register. The entry registers of the break address are
assigned to
, , and . Each bit of address corresponds to each
bit position, writing to
, , and is performed without shifting. The
corresponding area is the 1MB space of ROS1 and ROS2.
CPU MPCA7
A0~23
D0~D7
NMI
SSPRQ
D0~
D7
A23~
A0
BAR 0
BAR N
REGCS
Decode
Comparator
Coincide
Coincide
SPE
(Enable register)
SSPRQ
(NMI)
Control signal
ROMCS
O
N
1
2
3
4
FFFF00
H
1
2
3
4
5
6
7
BAR0
BAR1
BAR2
70
1 2 3 4
A19 A18 A17 A16 A15 A8 A7 A2
EN
Upper bits Intermediate bits Lower bits Enable register
EN (bit7) = 1 Enable
= 0 Inhibit
Don't care for "-----."
< BAR composition >
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