Sharp HT-M700H - Page 15

HT-M700H
4 – 4
MX29LV16
FLASH
U16400B
SD-RAM
SERIAL
EEPROM
ES6698FD
DECODER
SLDC
DEFCT
SVREF21
RFO
DB6 DB1
LD1
LA12
TESTAD
DOE# MA8
LD6
LA4 LA18SCLK
XSC L K
DB11
MA2
LA3
SCSJ
XSC S J
MA5 MA11
MA4 DMA4
LA17
LA2
SDATA
XSD A T A
OPEN
DB3
LA6 LA7 LA19 WRLL# LA14
MA0 DMA0
LA1
TRACK
DB9 DB13 DB5
LA0
LA5 LA11
DSCK MA10
LD5 LD2
LA10SPINDLE
AUX0
RAS2# MA9 MA0 RAS0# DQM
DB8 DB10 DB14
MA6
RFRP
CAS# RAS1#
LD7
RESET#
SVREF15
DB12
LA9
DWE#
DB15
MA3
DB4 DB0
LD3
MA4
DB2
LD4
TEI
SLEGN
CS0# MA7
MA3 DMA3
LCE#
LA8
MA1
DB7
MA11 DMA11
LA13 LA15 LA16
FOCUS
RFRP
LA13
DSCK
SLEGP
WRLL# LA4
DB15
RESET#
DEFCT
LD4 LCS3#
CEI
FDAC1
SLDC
TR1
TBCK
LA0 LA3 LA6 LA10 LA11 LA17
DB1
DB3
DB0
SPDIF
FDAC1
DQM
TSD0
COMP
LD1 LD0 LCS2# LA21
DB10
DB6
RBCK
UDA C1
VS33_PL2
RSD LOE# LA7
DB8
TR2
SVREF15
LD7 LA15
DB12
DB5
DWE#
SVREF15
UDAC1
LA5 LA12
DB11
TSD1
TWS
GNDV
RSET
VREF
VD33_PL1 RWS LD3
VDAC1
DCLK
AUX0
TESTAD
LA14
DB14
RAS1#
LA2 LA18 LA19
DB13
DB4
CS0#
SBAD FEI
XIN
SVREF09
SVREF21
CDAC1
LD5 LA8
DB2
CDAC1
VDAC1
LA1
DB9
XOUT
MCLK
VCC33V
LA9 LA16
DB7
DMA8MA8
DMA10MA10
TSD2
LD6 LD2 LA20
LA20 LCS3# LCS2#
YDAC1
YDAC1
DMA2MA2
CAS#
RAS0#
RAS2#
DOE#
LD0 LOE#
DA DA
EAUX03 EAUX02 EAUX01 EAUX00 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 AUX1
SPDIF_IN
FLASHVCC
RFGND
TWS TBCK
AUX1
DMA1MA1
DMA5MA5
DMA6MA6
DMA7MA7
MA9 DMA9
VCC33V
DIP
TR1 TR2
SPINDLE3
SDEFCT3
OPEN3
SLDC3
FOCUS3
SVREF213
SVREF153
TRACK3
SLEGN3
MIRR3
TEI3
RFO3
CEI3 FEI3 DIP3
SBAD3
SCSJ3
SDATA3
SCLK3
INSW3
HOMESW3
OUTSW3 DRVSB3
UDA C CDAC YDAC VDAC
FDAC
SPDIF TBCK MCLK TSD2 TSD1 TSD0 TWS
RWS RBCK RSD
RESET#
MOCTL
LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
3 MOCTL
3CLOSE
HFMVSW3
BIAS3
EAUX03 EAUX02 EAUX01 EAUX00 AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7
SPDIF_IN
PLL33V
RF33V
VCC33
VCC
GND
VCC33
GND
GNDV
GND
GND
VCC20
VCC33V
RFGND
VCC33
GND
GND
PLLGNDRFGND
VCC20
VCC
GND
FLASHVCC
GND
VCC33
VCC33
U1A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
VD33
XIN
XOUT
DCLK
DMA0
DMA1
DMA2
DMA3
VS33
VD33
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
DMA10
VS33
VD33
DMA11
DCAS
DCS0
DCS1
DRAS0
DBANK0/ DRAS1
VSS
VDD
DBANK1/ DRAS2
DCKE/DOE/TDMTSC
DWE
DB0
DB1
DB2
VS33
VD33
DB3
DB4
DB5
DB6
DB7
DB15
DB14
VS33
VD33
DB13
DB12
DB11
DB10
DB9
DB8
DSCK
VS33
VD33
DQM
LA21 LA20 LA19 LA18 LA17 LA16
VS33
VD33
LA15 LA14 LA13 LA12 LA11 LA10
LA9
VSS
VDD
LA8 LA7 LA6 LA5 LA4 LA3
VS33
VD33
LA2 LA1 LA0
LCS0
LCS1 LCS2
VSS
VDD
LCS3
LWRLL
LOE
LD0 LD1 LD2 LD3
VS33
VD33
LD4 LD5 LD6 LD7
RSD/TDMDR
RBCK/TDMCLK
RWS/TDMFS
VD33_PLL
VS33_PL
YUV1/VREF
YUV3/COMP
YUV4/RSET
YUV7/FDAC
YUV6/VDAC
VD33_DA
VS33_DA
YUV5/YDAC
YUV2/CDAC
YUV0/UDAC
TWS/SEL_PLL2
TSD0/SEL_PLL0
TSD1/SEL_PLL1
VS33
TSD2
TSD3
MCLK
TBCK
SPDIF/SEL_PLL3
SPDIFIN
VD33
VS33
XSWBLCLK
XSWBL
XSLG
XSIP2
XSIP1
XSFLAG[0]
XSFLAG[1]
XSFLAG[2]
XSFLAG[3]
VSS
VDD
XSTEXI
XSTESTAD
XSSBAD
XSFEI
AVSS_AD
XSCEI
XSTEI
XSRFRP
AVDD3_AD
XSVREF[21]
XSVREF[09]
XSVREF[15]
XSIREF
AVDD3_DS
XSIPIN
XSRFIN
XSRFIP
XSDSSLV
AVSS_DS AVSS_PL XSPD O F T R1 XSF DO XSF T ROPI AVDD3_PL XSPL L FT R1 XSPL L FT R2 XSVR E F 0 XSAW R C AVSS_DA XSRFRPCTR XST RA Y AVDD3_DA XSSPINDLE XSF OC U S XSSL E G P XSSL E G N XST RAC K XST EST D A XSF GI N XSPHO I SXCSJ XSD A T A XSC L K XSD F CT XSL DC XSSPD O N VD33 VS33 XGPIO [ 9 ] XGPIO [ 8 ] XGPIO [ 7 ] XGPIO [ 6 ] XGPIO [ 5 ] XGPIO [ 4 ] EAUX03 EAUX02 EAUX01 EAUX00 VSS VDD AUX0 AUX1 AUX2/ HSYNC AUX3/ VSYNC AUX4 AUX5 AUX6 AUX7 RESET VS33
U3
24C02
12
3
4
5
6
7 8
S0 S1 S2 GND SDA
SCL
WC
VCC
Y1
27 MHz
TP2
U5A
1 2 4 6 5 7 3 8 10 12 11 13 9
15 16 17 18 19 35 22 23 24 25 26
14 28
29 30 31 32 33 34 36 37 38 39 40
43 42 44 46 45 47 49 48 50 52 51 53 41
20 21
27 54
VCC DQ0 DQ1
VSSQ
DQ2 DQ3
VCCQ
DQ4 DQ5
VSSQ
DQ6 DQ7
VCCQ
DQML WE
CAS RAS CS A11 A10 A0 A1 A2 A3
VCC
VSS
A4 A5 A6 A7 A8 A9 NC CKE CLK DQMH NC
VCCQ
DQ8 DQ9
VSSQ
DQ10 DQ11
VCCQ
DQ12 DQ13
VSSQ
DQ14 DQ15
VSS
BA0 BA1
VCC
VSS
U6A
V6300C
RESET
1 2 3 4
5
NC GND NC R E S
VDD
U2A
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W
RP VPP DU/WP NC NC A17 A7 A6 A5 A4 A3 A2 A1 A0
E
GND
G
DQ0 DQ8 DQ1 DQ9 DQ2
DQ10
DQ3
DQ11
VCC DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A_1
GND
BYTE
A16
TP1
Figure 4-4 BLOCK DIAGRAM (4/14)