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Sharp MZ-5500 Tehnical Manual

Sharp MZ-5500
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3.
Interrupt
circuit
:3
-1.
Inter
t-tApt
(;
H-C.t.(,.t
i)
Circuit
description
Two
chips
of
8259A PIC
are
used
for
the
MZ-5500/5600
series,
and,
their
circuits
are
shown
below.
A
high
on
the
interr
"
upt
request
line
of
the
8259A
Interrupt
Controller
applies
an
interrupt
to
device.
As
the
state
of
the
mask
and
priority
of
the
interrupt
input
is
interrogated,
the
INT
signal
is
issued
to
CPU.
Because
the
INTR
line
of
the
CPU
is
asynchronous,
an
interrupt
request
can
be
accepted
at
any
time
unless
it
has
been
prohibited
by
the
software.
When
the
CPU
receives
the
interrupt,
INTA
i8
returned
via
the
8288
Bus
Controller.
To
which
the
8259A
forces
the
da
ta
bus
high
impedance.
As
the
second
INTA
is
sent
from
the
CPU
via
the
8288,
an
8-bit
vector
is
sent
on
the
data
bus.
y,"",
U
IHT1I I
Jr-Tm
lI-nrT
~
II~
~
iI-IR
1J-filC
--rz
11--
Jr-1r
iT=1i
Jr-T
Tr-T
IlAI
!lA'
L-~_""-.J-------'--fTR"T~
sr
....
SI
s~
L e
ge
n
cl:
. T
he
\J
m a r k
re
p
re
sen
t s t h e
6.
8
kn
pu
11
u P
re
s
ist
0 r .
Timings
cu
11.
IIrT
IIrTA
Fig.3-1
Interrupt
circuit
diagram
and
timings
2(,

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Sharp MZ-5500 Specifications

General IconGeneral
BrandSharp
ModelMZ-5500
CategoryDesktop
LanguageEnglish

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