Sharp MZ-5500 Tehnical Manual

°DMA channel 1 (SW is not used for the channel 2)
T4 .. rTI
T1I TW TW (TI)
ClK86
( 8!o/H, )
C1 .K37
I ~ WH ~)
HRQ
HlUA
UACK I
READY
(
([~)
1-Hl; E.
TIlr
:rnnr
(~EVI,l)-==========-,i~----~============~===================x~
TC~ _
(11 :J ~ 5!. )
ADR
CPU v..ddress
I,WA l14J(e~!ö
DATA
eWO
I
- ________ -1
UItAO
UWA CPmII\uoJ
ROY
r - - - - - - - - - - - - - - -,.ri/'--------------,
(8284)
QSince some of signal names differs between the MZ-SSOO and MZ-S600, the
signal name given parenthesized 1s for the MZ-SSOO.
°The CPU clock CLK86 and the DMA clock CLK37 are completely async clocks.
Fig.6-2 DMA timing
"
from a channel, the DMAC issues the hold request Upon rece1v1ng of DREQ
. signal (HRQ) ~o the CPU. As the HOLD conversion circuit receives this
sjgnal, it makes the CPU in the non-ready state and the system bus is
released. ·At the same time, the hold acknowledge signal (HLDA) and the DMA
enable signal (DMAE) are returned to the DMAC to perform the DMA transfer.
The '8237. DMAC controls DMA transfer of any 16-bit area (64KB) represented by
address . signals, AO - A7, and A8 - AlS which ' latcl~ DBO - OB7 with
ADSTB at the beginning of the DMA transfer. Also, lD4 - 7 latch signals of
1/0 (50H) are used as A16 - A19 in order to cover up the 1MB memory address
space of the 8086 CPU.
The DMAC goes ready with the DMA transferred memory ready signal, but the
ready si~nal returned with 0 wait is automatically attached with 1 wait.
However, it is 0 wait at all time during refreshing.
\1 j
~

Sharp MZ-5500 Specifications

General

Brand	Sharp
Model	MZ-5500
Category	Desktop
Language	English