Sharp MZ-5600 - Page 16

....
C1I
I
Block
diagram
~------------~
~~----------------------~--------~
Address
bus
or
bidirectionel
data bus
BHE/S7~
AD
18
AD
12
AD
11
Interrupt
acknowledge ( I
NfA)
Write
control
(n')
Read
control
Data transfer
control
Data send/receive
(DT
IR)
control
__
Data enable
DEN
Address latch enable
(ALE)
8
Address adder ( B I U )
os
(16)
ss
(16)
ES
(16)
I Segment register/
I P
(16)
Instruction
pointer
.6-byte
-'-,;..;..---f
l
instruction
>
~
0 )
Quaue
buffer
.
1
t
I
Timing
status
-------'-I------------r----...J-f------:r---:r-......:-.-j~.
and
control
'f
logic
16
16
16
1------
16
_L
J_
~
- -
--
AH
(8)
AL
(8)
BH
(8)
BL
(8)
CH
(8)
CL
(8)
DH
(8)
DL
(8,)
SP
(I6
)
BP
(I6
)
SI
(I6
)
DI
(I6
)
General-purpose
register
file
Parallel 16-bit
I logical
unit
Execution
unit
(EUI
Fig. 12
INTR
Maskable
interrupt
request
input
Non-masklble
interrupt
Reset
input
request
input
~
READY Ready
input
1---(23)
TEST
Test
input
RQ IGTO} Request grant
:3Q)
RQ
IGTI
output
(MaxI
1)
,(
HOLD)
Hold
request
input
(MinI
(HLDA)
Hold acknowledge
output
CLK
~MN/MX
~~
P--(28)S2
Clock
input
(MinI
Mode select
input
Lock
request
output
(MaxI
} Queue status
output
(MaxI
}
"'M
00""'
IM'"
;1