o
811H.,
611Hz.
aWAIT
Tl
CLK8B
ADR
ALE
Tt
TW TW
o 8MHz XACK (In the cell
ofXACKl1
0 WAIT)
Tl
Tt
TI
T1I
TC
=~
_"lIlY
_
o 8MHz
XACK
(In the
C8II
of
XACK
I1
1
WAIT'
Tl
TI TI
T1I T1I
TC
TI(
T
J)
~~
• IIIBI
'ltIJr
T1
T2
T8
TW
Tt
~~
o Time out ready
Tl
Tt
Ta
TW
TW TW
T4
CLK8B
ALE -I"i_==-=--==-""""'
___________
...JIL
T-OUT
_______
---s==:--::lllO:.;.I'..:.S
__
.....J
1
.......-----
.....
L--
4-10. Hold conversion circuit
1. Block diagram
8088-2
CPU LS878
LSIM/i
LS848
8237
DMAC
(1)
When
a
DMA
transfer request
signal
DREQ
is
issued
to
either
of
channels 0 through 3, the DMAC
sends
the
hold request signal H
RQ
to
the hold conversion circuit
if
that the channel
is
not
masked.
(2)
When
in the
CPU
address
cycle (*SO, *S1, *S2,
*LOCK
are
all
"1")
or
during
bus
access,
the hold conversion
circuit returns
to
the DMAC the hold acknowledge
signal H
LDA
at the final cycle (T4). And the
CPU
add-
-24-
ress
bus, data
bus,
and command
bus
are
isolated from
the system
bus
to
enable the
DMA
bus.
(3)
At
the
same
time, AEN
of
the 8284A
is
enabled
to
k'eep
the
CPU
in the
not
ready condition.
If
the
CPU
should go
into
the
next
bus
cycle,
it
awaits
for
return-
ing
of
bus
control while executing the
wait
cycle.
(4)
DMA
transfer
is
dona under the control
of
the 8237A.
(6)
As
the DMAC
releases
HRQ
upon completion
of
DMA
transfer, the system
bus
is
changed from the
DMA
bus
to
the
CPU
bus and the wait circuit
is
reset after
enabling the
8284A
again.
(6) The
CPU
executes the
wait
cycle on the local bus, but
acts
as
if
the
bus
cycle started from
T1
on the system
bus
after reset
of
the
wait circuit.
5.
MEMORY
CONTROL
LOGIC
5-
,lhiP
selection
(1) Block diagram
(2) DescriPtion
Fig.
26
If
the IOACC signal
is
high,
each
ROM
and
RAM chip
is
selected. The following
shows
the relationship
between the device
address
and
the chip selected:
Dynamic RAM-D
=
AfS.A
1B.A 17
(ODODOH
to
1
FFFFH)
Dynamic RAM-1 =
AfS.A18.A17
(20ODOH
to
3FFFFH)
CS·IPL = A19.A18.A17.A16.A15.A14
(FCOODH
to
FFFFFH)
5-2 Address multiplexer
(1) Block diagram
'iiACK2
AO
-t----L..-I
AI6------I
Fig.
27
(2) Description
s
LS257
AXO
AX1
L.-_-'
The
address
multiplexer provides A
1-A
16 outputs
when
accessing
the RAM, and
AO-A
15 when refresh·
ing
it.
This
is
needed
because
the
address
viewed
from
I
'10
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