13. SOFTWARE TIMER
13·1
Block
diagram
IORQ
1mi
~
mE'!"
2A576I11z
CHO-8
1---r~f-~l"Imr
ZC/T02
.......
....,.....+---I-... m
~-+-r-+-~.~
~
RS232C(B)
clock
RS232C(A)
clock
Refresh
~
CLK/TRrJ~.--.J
L....I--
......
1OIRi'
L..--4--
.....
·m
L......,.--+--
......
1lf
~.
__
L-_-I
CH
4-7
It
13-2
Operational
description
Two
Z80A
CTC
are used for
the
softwarl! timer, and it has
eight
channels; each one having specification described
in
the next paragraph.
Timing
control circuit
is
adopted
in
order
that
the
8086
CPU
may control I/O read, write, interrupt acknowledge,
and
interrupt restore cycles of
the
Z80A CTC.
As
the
8086
,
CPU
has
no interrupt acknowledge and interrupt restore
'
cycles,
the following procedure
is
given using the I/O port
!
(*CSAKC,
*CSRET). For
the
interrupt acknowledge cycle,
the interrupt vector
outputted
from the
CTC
is
sent
to
the
AL
register when read through
the
I/O port (240H). For
the interrupt restore cycle,
the
data equals
to
"RET1"
of
the
280
CPU
when writing
"O~or
"04DH"
to
the
I/O
port (260H).
13·3
Channel
description
CH
No.
I/OADR
MODE PRESCALE
INT
0
210H
Timer
1/16-
X
1 211H
t t
X
2
212H
t t
X
3
213H
Counter
----
0
4 214H
t
----
0
5
215H
t
~
0
6
216H
t
=:::::::::::
0
7
217H
t
----
0
Time Constant etc
2
1
9600 b/s
2
4800
4 2400
8
1200
16
600
32
300
64
'150
87 110
0.832
mS
- 213
mS
0.052
mS
- 13,313
mS
0.832
mS
- 213
mS
0.832
mS
- 213
mS
3.328
mS
-
852
mS
-51-
Refresh
timer;
153/2
ms
RS-232-C
CHA
TX,Rx
RS·232-C
CHB
TX,Rx
System Timer
Reserved
For
SEEG version
only
Reserved
Reserved
-
MZ'"'"5600
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