13-4 Interrupt processing
For the Z80A
CPU,
interrupt
is
processed by the hardware,
and for the
MZ·5600, it
is
processed by
the
software.
Because the inte"rrupt controller 8259A control interrupt
to
the MZ·5600, it needs
to
issue the interrupt terminante
command
(EOI)
to
the 8259A
in
case it
is
possible
to
accept an interrupt of higher priority at the end
of
the
interrupt processing-routine.
Execution
of
)
interrupt
I
MOV
DX,240H
~Dummy
IN
AL,DX
I
I
Distinction
of
interrupt
I
MOV
DX,2S0H
~Dummy
MOV
AL,OEDH
OUT
DX,AL
MOV
AL,4DH
OUT
DX,AL
13-6·1 Timing chart
Tl
T2
TB
TW
TW TW
TW TW TW
TW
TW TW TW
TW
TW
TW TW
TW
T4
CLK8B
Rnd
CTe
DATA
OUT--~=======:jc======~>--
I
>--
l
·=~
-
,."."
~==============~======================~r---====
H------------------------------------------
13-6·2 Timing chart
Tt
T2 T8
TT!'
TW
TW
TW TW TW TW
TW
TW TW TW TW
TW TW
TW
T4
eLK.
I
interrupt
ecknowtodge
cycle
Execution
of
interrupt
I
MOV
AL,20H
~
1;01
command
OUT
30H,AL
STI
I
C
IRET
)
13-5 Distinction
of
interrupt channel
The Z80A
CTC
issues the interrupt vector
in
the interrupt
acknowledge cycle.
As
the vector contents are set
in
the
AL
register when
the
MZ·5600 executes the dummy interrput
acknowledge cycle, the interrupt channel can
be
known
from the contents.
However,
as
the vector "OH" has already been set
to
the
CTC·', the CTC·2 must have the vector
of
"08H"
set.
Ch
VECTOR
3
06
H
4
08
H
5
o AH
6
o CH
7
o
EH
eTe
DATA
OUT
--/------------------..:.C=========:::J
~-~==t===================================~c
Interrupt
retum 1'miJr
cycle
~:cE==~iQ~~~~========~-
8IIDATA
OUT-
-52-
To Next Page
Loading...
