13·7
Z80A
CTC
crc pin configuration
DO
t
CPU
data bus
Dl
D2
D3
D4
CLK/TRGO
ZC/TOO
CLK/TRGl
ZC/TOl
Channel
D5
signal lines
D6
D7
CSO
CSl
CTC
CHIP
control lines
ENABLE
Ml
IORQ
RD
RESET
+5V
GND
Z-80ACTC
CLK/TRG2
ZC/T02
CLK/TRG3
~
Interrupt
!INTENA~rI
contrail
inos
IN
11
INTENABLE
OUT
,
Fig.
61
Z-8OCTC
pin descriptions
00·07: Bidirectional, three-state
CPU
data bus.
CSO-CS1:
Active high channel selector inputs. The CTC
creates a
two
bit binary address code from these
selector inputs
to
select
one
out
of
the
four
independent
CTC channels
(a
truth
table
is
shown below).
CSl
CSO
ChO
0 0
ChI
0 1
Ch2
1
0
Ch3
1
1
CE:
Active low chip enable
input
/
..
Clock(cf»:
System clock input.
t;
M1:
Active low
input
indicating machine cycle 1 from
the
CPU.
If
M1
and RD are
both
active, it
indicates
the
CPU
has
fetched
an _instruction
from memory.
If
M1
and
10Ra
are
both
active,
it indicates
the
CPU
is
in
an
interrupt
ackr,ow-
ledge
cycle.
IORO:
Active low I/O request
input
from
the
CPU. The
10Ra
is
used
in
conjunction with
the
CE
or
RD
when data
or
channel control words are
to
be
transferred between
the
CPU
and
the
CTC.
During a CTC write cycle,
the
lORd
and
CE
must be
both
one,
and
RD
mu~be
zer~uring
a CTC read cycle,
the
10Ra,
CE,
and
RD
must
be
all
active
to
place
the
contents
of
the
down
counter
on
the
10
data
bus. If
the
10Ra
and
M1
and
both
one, it indicates
the
CPU
is
in
an
interrupt
acknowledge cycle.
Active
low
input
indicating
CPU
read cycle
status. The
RD
is
used in conjunction with
the
10Ra
or
CE
when
data
or
channel control words
are
to
be transferred between
the
CPU
and
CTC.
-53-
IEI:
IEO:
INT:
-
MZ-5600
Active high
interrupt
enable input. This signal
is
used
to
create an
interrupt
control daisy chain
within
the
system.
If
there
is
more
than
one
peripheral device which can be a source
of
an
interrupt
within
the
system,
their
order
of
priority
is
determined by using
the
IEI
and
IEO.
Active high
interrupt
enable
output.
This signal
is
used
in
conjunction with
the
IEI,
to
create a
daisy chain used
to
determine
the
order of
priority of interrupts within
the
system. The IEO
is
set high only if
the
IEI
is
high, no channel
within
the
CTC ,is requesting interrupt, and
the
CPU
is
not
servicing any
interrupt
from
the
CTC.
Open-drain, active-Iow
interrupt
request
output.
This signal goes active if
the
IEI
is
high and
the
down
counter
on any
of
the
CTC channels which
is
programmed
to
enable an
interrupt
is
counted
down
to
zero.
RESET: Active low reset input.
ClK/TRG3-ClK/TRGO:
External clock/timer trigger
input
with user-selectable active level (high or
low). There are four
ClK/TRG
pins which
correspond
to
the
four independent CTC chan-
nels.
In
the
counter
mode,
the
counter
is
de-
cremented
by 1 each time an active transition
(positive
or
negative)
is
applied
to
this pin.
In
the
timer
mode, clock operation
is
initiated by
an active transition
applied
to
this pin.
ZC/T02-ZC/TOO: Active high zero-count/time-out
output.
The CTC has
three
ZC/TO pins which correspond
to
the
CTC channels 2, 1, and 0, respectively
(channel
3 has no ZC/TO pin due
to
package
restrictions).
In
either
the
counter
or
timer
mode, these pins
deliver an active high pulse
when
the
counter
has
counted
down
to
zero.
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