...
'
,
t
7-4
J.LPD8237
A DMA controller
(1) Highlights
(2) Pin configuration
1)
Independent DMA-request enable/disable control.
2) Four independent
DMA
channels.
3) Automatically initializes individual channels.
4) Memory-to-memory transfer capability.
(Not
used
for
MZ5600)
5) Memory block initialization.
6) Address increment/decrement.
7)
Transfer rate
of
up
to
1.6MB/s. (2.5MB
for
com-
pressed
timing).
8)
Can
be
expanded
directly
to
any number
of
chan-
nels.
9)
EOJ5
input
for
termination
of
transfer.
10) Software
DMA
request.
11)
Variable active levels on DREQ and
DACK
signal
lines.
(3)
Block diagram
DEC
INC/DEC
ToP
TEMP'WORD
TEMP
ADDRESS
COUNT
RE~06)
REQ(I6)
RESET
CS
READY
CLOCK
IOR
IOW
lmIm
MEiiW
("0
READY
HLDA.
ADSTB
AEN
HRQ
~
CLK
RESEr
I:Wl<2
Dl\CK8
I:RFX)8
~2
mEQl
mEQO
GND
AO-A7
AEN
&
READ
BUFFER
READ/WRITE
BUFFER
ADSTB
BASE
I
BASE
CURRENT
I
CURRENT
CONTROL
ADDRESS
I
WORD
ADDRESS
I
WORD
MEMR
I
COUNT
I
COUNT
IIEMW
I
06) 06)
I
(16)
iOR
IOW
DREQ
Internal
HLDA
data
bus
HRQ
WRITE
BUFFER
DACK
MODE
(4X6)
,.
-33-
20
.,
1
0
<
COMMAND
CONTROL
-
MZ-5600
A7
A6
A5
A4
IDP
AB
A2
Al
AO
Vcc+5V
000
001
DB2
008
m4
Dl\CKO
Dl\CKI
DB5
006
007
Fig. 38
AO-AS
A4-A7
DBO-DB7
To Next Page
Loading...
