Sharp MZ-5600 - Page 41

MZ-5600
8-8 Foe LSI (#LP0765)
#LPD765 Pin configuration (top view)
RESET
AO
DBO
DBl
DB2
DB8
DB4
DB5
DB6
Fig. 45
RESET:
RD:
WR:
VCC
RW/SEEK
LCT/DIR
FLTR/STEP
HDLD
READY
WPRT/2SIDE
FLT/TRKO
PSO
PSI
WDATA/
usa
USl
SIDE
MFM
I
WE
SYNC
RDATA
WINDOW
WCLK
Reset
Read
Wri
te
CS : Chip
Select
AO: AO
DBO' 7 : Data Bus
DRQ: DMA Regurst
DACK: DMA Acknowledge
TC:
Terminal
Count
INDEX:
I rrlex
INT:
Interrupt
Reguest
flJ:
Clock
GND: Ground
WCLK:
Wri te Clock
WINDOW:
Data
Wirrlow
RDATA:
Read
Data
SYNC: VFO Synchronize
WE:
Wri te Enable
-40-
#L
P
D765 Block diagram
DBO-7
DRQ
DACK
INT
RD
WR
AO
TC
RESET
CS
"-
MFM:
SIDE:
USO,l :
WDATA:
PSO,l :
FLT:
TRKO:
WPRT:
2S I DE :
READY:
HDLD:
FLTR:
STEP:
LCT:
DIR:
RW/SEEK:
MFM Mode
Side Select
Uni t Select
Wri te Data
Pre Shift
Fault
Track 0
REGISTERS
SERIAL
INTERFACE
CONTROLLER
DRIVE
INTSRFAC
CONTROL
LE
Fig. 46
Wri te Protected
Two Side
Ready
Head Load
Faul t Reset
Step
Low Current
Direction
Read Wri te/Seek
..... --WCLK
t--_WDATA
t--_WE
t--_PSO
t--_PSI
I+---RDATA
1+--- 'NI NDOW
t--_SYNC
READY
'NPRT/2SIDE
INDEX
FLT/TRKO
usa
US!
IIFII
RW/SEEK
HDLD
SIDE
LCT/DIR
FLTR/STEP