Sharp MZ-5600 - Page 57

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MZ-5600
Pin configuration
2xCCLK
DBIN
HSYNC-REF
VSYNC/EXSYNC
BLANK
RAS
DRQ
Block diagram
DACK
RD
WR
AO
DBO
DBI
DB2
DBS
DB4
DB5
DB6
DB7
GND
J,lPD7220
40
39
Vcc
AI7(CSR-LC4 ) (CSR-lMAGE )
AI6(LCS) CA't·BLlNK-CLC)
ADI5(LC2)
ADI4(LCl)
ADIS(LCO)
ADl2
AD 11
AD 10
AD9
AD8
AD6
AD5
AD2
ADI
ADO
LPEN
( ):
[ 1:
For text mode only.
For text and text graphic integral mode
Fig. 67
AI7(CSR-LC4) AI6(LC3) ADIS ADI4 ADIS ADO-
BLANK
VSYNC/
EX. SYNC
HSYNC-
REF
LPEN [CSR-UWiE) CAT. BLINK- (LC2 )(LCI )(LCO) ADI2 RAS OOIN
CLC)
Sync. sig nal generator
~~
2xCCLK
AO
RD
CPU interface/
I/O
Command
Data
WR
DMA controller
interface
control
I
RAM
FIFO
ROM
(16 x 8)
DRQ
(16 x 9)
(128x14)
DACK
0 0
(
):
DBO-DB7
+sv
GND
Bit count
Fig. 68
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