Sharp MZ-5600 - Page 73

I
r3
I
VDC1 timing
for
display cycle (2)
a
of
HOOl
2XCCLK
~
\ I \ I
,-
CPU
\ {
--------'
CPU
Timing
-
-----------------.~--::~:;.;-------------------------====================================~~=========
H5afarH015and
OE
--..I
I!::=
10.1--67.2 X
H025
are latched
X
--011-
~7-1
•.
'
.-
Q
of
HOI.
======---------------------------------------------------i\
if
refresh
I (refresh)
{
~
10.1-5.5--1
j.-
I
I-
"I
L I
~
I
9.2-489
320
mode
~
1UiCK
J U
----I
I-- 9.8-42.1
U U
U",--
U U
U",--
U U U
V-
~
~
9.9--62.6 a
of
HOll
---------------------------------------------------~L
(S/L mask)
The
following
timing
relationships are given
by
forced arrangement.
Fig.
105
S7L
~
--I
r-
-0.8-10.8
ns
I
--~--
~\
I
OOTCK
CAS 1 ----
r-
~xDOTCK+8.4ns
miD
Figs. 106, 107
[5.
~
8