Sharp PC-1350

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Pin No.
Signal name In / Out Description
Standby= power off
1 A01
Out
(AO) Address bus line. High during standby.
2 R / W
Out Write clock . Normally high.
3
cj> AL Out
Low order bit address latch. Normally h i gh . Clock used to latch the low order 8 b i ts sent on the data
bus line which is used in sending 16 bits address signal when using a large capacity ROM.
4 TES
In Test pin . Normally low.
5
¢ 1
In
Osc i llator input .
6
¢ 0 Out Osc i llator output.
7 RES In
Reset input . Res e t wh en high. Normally pulled down to low level.
8
X i n In
CE - 124 microcassette tape recorder option signal i nput (MTin) .
9
ON
In ON [BREAK] key i nput . Normally pulled down to l ow leve l.
jBRKI
10 Xout
Out CE-124 m i crocas s ette tape recorder option and buzzer signal output (MTout1 ) .
11 Dis
Out LCD dr i ver control signal.
12 HA Out
LCD d r iver clock . Low during standby . 2 KHz pulse generated during d i sp l aying.
13
IAB In / Out
Key signal i np u t/ key st r obe output signal. Low during standby . Pu l se generated when key is pressed in
the low level.
14
IA7
In/Out
Key signal i nput / key strobe output signal . Low during standby . Pulse generated when key is pressed in
the low level.
15
IA6
In / Out
Key signal input / key strobe output signal. Low during standby . Pulse generated when key is pressed in
the low l e vel.
16 IA5 In / Out
Key signal input / key strobe output signal. Low during standby. Pulse generated when key is pressed in
the low level.
17 IA4 In / Out
Key s i gnal input / key strobe output signa l. Low during standby. Pulse generated when key i s pressed in
the low level .
18 IA3 In / Out
Key signal input / key strobe output signal. Low dur i ng standby. Pulse generated when key is pressed in
the low leve l.
19 IA2 In / Out
Key signal input / key strobe output signal. Low dur i ng standby. Pulse generated when key is pressed in
the low level.
20 IA1 In / Out
Key signal input / key strob e output s i gnal. Low dur i ng standby. Pulse gene r ated when key is pressed in
the l ow leve l.
21 188 In
ACK signal. Enable signal when the 1/0 (PCU) reads data from the CPU .
22 187 In
Data In (Din) s igna l. Se ri al data input signal from the PCU (bit term ser i al handshaking).
23 186 In
SIO [CD] . D e t ec tion of a send request from the other end.
24
185
In SIO [ CS] . Dete c tion of send enab l ed from the other end.
25 184
In SIO [RD] . Re c eive data .
26 183 Out
SIO [RR]. Sendi ng of rec eive enabled from this end . Low during standby
(buffered by gate alley).
27 182
Out SIO
[RS ].
Send i ng of s en d request from this end . Low during standby (buffered by gate alley).
28
181 Out
SIO [ER]. Goes high by the e x ecut i on of OPEN command. Low dur i ng standby (buffered by gate
alley) .
29 VM
In
LCD power supply .
30 VA In
LCD power supply.
31 GND In
Power supply
32 H1
Out LCD backp l at e signa l. High impedan c e dur i ng standby . 4 - level pulse dur i ng displaying.
33
H2 Out
LCD backplate signal. High impedance during standby. 4-level pulse during displaying .
34 H3 Out
LCD backplate signal. High i mp e dance during sta n dby . 4 - level pulse dur i ng d i splaying.
35 H4 Out
LCD backplate s i gnal. H i gh i mpedance dur i ng standby. 4 - level pu l se during displaying.
36 H5 Out
LCD backplate s i gnal. H i gh i mpedance during standby. 4-level pulse during displaying .
37
H6 Out LCD backpla t e s i gnal. High impedance during standby . 4 - level pulse during display i ng .
38
H7 Out LCD b a ckplat e signa l. High imp e dance during standby. 4-level pulse during display i ng .
39 HS
Out LCD backpla te signa l. High impedance during standby . 4-level pulse during disp l ay i ng.
40 H9
Out LCD backp l a t e signal. High impedance during standby . 4 - leve l pulse during display i ng .
41 H10 Out LCD backplate s i gnal. H i gh impedance dur i ng standby. 4 - level pu l se during d i splay i ng .
42 H11 Out L CD backpla te signal . H i gh i mp e da n ce during standby . 4 - level pu l s e during displa y ing .
43
H12 Out LCD backplate s i gnal. High impedance d u ring standby . 4-level pulse during displaying.
44 H13 Out LCD backplate s i gnal . High i mp edance during standby . 4 - leve l pulse during displaying.
45 H14 Out LCD backplat e sign al. High i mp e dance during standby. 4-leve l pulse during display i ng .
46 H15 Out LCD backplate si gnal. High impedance during standby . 4 - level pulse du r ing displaying .
SC61860A 13 microprocessor signal description
8. LSI DESCRIPTIONS
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PC-1350