Siemens Simatic S7-1500H - Page 49

Event-driven program execution
4.1 Response time of the CPUs when program execution is event-controlled
Cycle and response times
48 Function Manual, 10/2018, A5E03461504-AD
Interrupt response times of the CPUs for hardware interrupts
The interrupt response time starts with the occurrence of a hardware interrupt event in the
CPU. The interrupt response time ends with the start of processing of the assigned hardware
interrupt OB.
This time is subject to system-inherent fluctuations, and this is expressed using a minimum
and maximum interrupt response time.
The following table contains the length of the typical response times of the CPUs for
hardware interrupts.
Table 4- 1 Response times of the CPUs for hardware interrupts
S7-1500
1511(F)-1 PN
1511T(F)-1 PN
1511C-1 PN
1512C-1 PN
1513(F)-1 PN
1515(F)-2 PN
1515T(F)-2 PN
1516(F)-3 PN/DP
1516T(F)-3 PN/DP
1517(F)-3 PN/DP
1517T(F)-3 PN/DP
1518(F)-4 PN/DP
1518(F)-4 PN/DP MFP
Interrupt re-
sponse times
Min.
100 μs
90 μs
30 μs
20 μs
Max.
400 μs
360 μs
120 μs
90 μs
S7-1500R/H* in RUN-Solo system state
1513R-1 PN
1515R-2 PN
CPU 1517H-3 PN
Interrupt re-
sponse times
Min.
100 μs
90 μs
30 μs
Max. 400 μs 360 μs 120 μs
* Additional information about cycle and response times of R/H CPUs is available in the section "Cycle and response times
of the S7-1500R/H redundant system"
ET 200SP
1510SP(F)-1 PN
1512SP(F)-1 PN
1515SP(F)-PC
Interrupt re-
sponse times
Min.
100 μs
100 μs
90 μs
Max.
400 μs
400 μs
360 μs
ET 200pro
1516pro(F)-2 PN
Interrupt re-
sponse times
Min.
90 μs
Max.
360 μs
The specified times are extended:
● If higher-priority interrupts are queued for execution
● If the hardware interrupt OB is assigned to a process image partition