Cycle and response times of the S7-1500R/H redundant system
5.5 Timetables for the RUN-Redundant system state
Cycle and response times
Function Manual, 10/2018, A5E03461504-AD
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Accuracy of a cyclic interrupt
Even if a cyclic interrupt is not delayed by a higher-priority OB or communication activities,
the accuracy with which it is started is nevertheless subject to system-dependent
fluctuations.
The following table shows the accuracy with which a cyclic interrupt is triggered:
Table 5- 7 Accuracy of cyclic interrupts
Accuracy of cyclic interrupts of the CPUs in the RUN-Redundant system state
A table with the accuracy of cyclic interrupts of the CPUs in the RUN-Solo system state is
available in section Time-driven program execution in cyclic interrupts (Page 40).
Interrupt response times for hardware interrupts
The interrupt response times of the CPUs start with the occurrence of a hardware interrupt
event in the CPU and end with the start of the assigned hardware interrupt OB.
This time is subject to system-inherent fluctuations, and this is expressed using a minimum
and maximum interrupt response time.
The following table contains the length of the typical response times of the CPUs for
hardware interrupts.
Table 5- 8 Interrupt response times for hardware interrupts
Interrupt response times of the CPUs for hardware interrupts in the RUN-Redundant system
state
Interrupt re-
sponse times
Min. 180 μs 150 μs 40 μs
A table of the interrupt response times of the CPUs in the RUN-Solo system state is
available in section Response time of the CPUs when program execution is event-controlled
(Page 47).
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