Sony CDP-C345 - Page 32

* IC BLOCK DIAGRAM
IC102 BA6392FP
CHI RIN
CHI F IN
VREF IN
VREF QUT
GNB
CH2 F IN
CH2 RIN
CAPA IN 2
CH2 OUT R
CH2 OUT F
GNA
1C451 BA6191
FIN 1
BUFF’
CHI OUT F (1) <]
CHI OUT R (2)
CONTROL
RIN 1 VREF 1 ()
VREF 2
THERMAL SHUTDOWN
CIRCUIT
F IN 2 (&)
RIN 2 (*)
MUT ING
CIRCUIT
CONTROL
VCC
QUT 2 (+) QUT 2 (-)
INTERFACE
QUT 1 (+)
OUT 1 (-)
CH4 OUT F
CH4 OUT R
VB IN
CH3 F IN
CH3 R_ IN
CAPA IN 3
CH3 OUT R
CHS OUT F
MUTE