Sony HBD-E490 - Block Diagram - MAIN Section

HBD-E190/E290/E490/E690
HBD-E190/E290/E490/E690
3131
5-3. BLOCK DIAGRAM - MAIN Section -
Ver. 1.1
5Y1
2Y2
Y0
10
A
AUDIO SELECT
IC5903
3Y
R-CH
L
R
AUDIO IN
\/1
J5901
ANTENNA
75:
FMCOAXIAL
R-CH
A5V (KARAOKE)
ASEL_0
69
CEC (TX/RX)
INVERTER
(AUDIO SELECTOR)
Q5901
SYSTEM CONTROLLER
IC6301
(1/3)
ST_SCL
46
ST_SDA
ST_RDS_INT
73
BD_RESET
CPU_XRST
BD_TEMP
1
3FRF1
BD DECODER
(FM RECEIVER)
IC101
CN104 (CND, PX)
CN102 (EXCEPT CND, AEP, UK, SAF, PX)
15LOUT
14ROUT
13DA
10CK
8IIC/RDSI
9
B
ASEL_1
70
R-CH
13
VinL
VinR
BCK
LRCK
SCKI
14
8
7
6
A/D CONVERTER
IC5904
BD DECODER
IC101 (3/3)
DOUT
9
C7
MICIN
AOSDATA4
B10
AOMCK
C10
AOLRCK
A10
AOBCK
45
MIC_DATA
58
MIC_CLK
PLUG_DET
63
NJU72341_POWER
61
57
89
81
X101
32.768kHz
X2
X1
19
18
OPTICAL
RECEIVER
IC5901
TV
OPTICAL
DIGITAL IN
1 RX0/RXP0(OPT)
RX1/RXN0(ARC)
DIGITAL AUDIO
PROCESSOR
IC8001
9
SCL/CCLK
10
SDA/CDOUT
16
GPO0
17
GPO1
18
GPO2
30
GPO3
2
AMP_D2
AMP_D3
AMP_D1
AMP_MCK
AMP_LRCK
AMP_BCK
ARC_SPDIF
CEC
C25
DIR_SCL
G24
DIR_SDA
15
AOSDATA0
D10
AOSDATA1
C9
C8
AOSDATA2
BUFFER
IC5905
RESET_
A21
TH6301
LCDRD D22
VDATA A23
VCLK A22
XIF_CS G21
GPIO0 D20
SYS_REQ E24
GPIO5 AB1
OPWRSB B21
FEGIO3U2
GPIO6
AB2
PCONT_FL25
PCONT3 38 PCONT3
PCONT2 37 PCONT2
PCONT1
PCONT1
36
BD_SDO
76
JIG_MODE1
82
BD_SDI
75
BD_SCLK
77
BD_CS
UPG_STATUS
OPWRSB
BD_IF_START
19
FE_EJECT
BD_IF_REQ
23
78
85
83
84
PCONT3
8CLK
9STB
7DIN
ND01
VACUUM
FLUORESCENT
DISPLAY
GR1 - GR8
SG1 - SG16
42 - 35 14 - 29
3 FL_DOUT
5 FL_CLK
68 FL_CS
FLUORESCENT INDICATOR
TUBE DRIVER
IC03
SIRCS_IN
REMOTE
CONTROL
SIGNAL
RECEIVER
IC30
1
T01
DC-DC CONVERTER
TRANSFORMER
D03, 04
RECT
VEE
SWITCHING
TRANSISTOR
Q03
16
8
UNSW +6V
AC_CUT
18
+6V REG
IC01
+3.3V
PANEL 6V
+3.3V
REG
IC6305
UNSW +12V
VOLTAGE
DETECT
IC6303
DCDC +6V
OVER
VOLTAGE
DETECT
Q5301
S301
KEY0
D6301
D6302
S40 ~ S42, S47
KEY1
95
KEY1
93
S43 ~ S46
KEY2
KEY2
92
KEY_INT
17
X6301
8MHz
XOUT
XIN
11 13
6LJQDOSDWK
: AUDIO
: TUNER
: MIC
MEMORY/HDMI
SECTION
(Page 30)
A
AMP
SECTION
(Page 32)
E
POWER SUPPLY
SECTION
(Page 33)
D
MEMORY/HDMI
SECTION
(Page 30)
C
MEMORY/HDMI
SECTION
(Page 30)
B
X8001
24.576MHz
XTO
XTI
12
11
2 4
H22
XDIR_INT
C24
DIR_GPO3
B25
DIR_GPO2
G25
DIR_ERROR
27
SDOUT1
28
OSCLK1
29
OLRCK1
31
RMCK
E23
SPDATA
B24
SPBCK
A24
SPLRCK
A25
SPMCLK
+3.3V REG
IC02
RESET
10
RXD1
30
ON CHIP DEBUG/CLK1
31
NO USE/RTS1
32
TXD1
29
RTS1
TXD1
RESET
RXD1
CLK1
CN6302
3
2
8
6
5
FLASH
PROGRAMMING
RESET
SWITCH
Q6301
POWER MIC DRIVER
Q5902, Q5903
J201
MIC 1
J202
MIC 2
MIC_DATA PLUG_DET
PLUG_DET
MIC_DATA
MIC_CLK
MIC_CLK
MIC
AMP
IC201
+
+
ELECTRICAL
VOLUME
IC203
RU
RU