signal is converted to an IP signal (conforming to 100GBASE-SR), and then the converted IP signal is transmitted to
the QSFP28 module.
Motherboard input (CNO-45 board [XKS-C9121, XKS-C9121N])
The SDI signal transmitted from the motherboard is input to the FPGA (IC2, IC3) in which Output Video Process is
added to this signal. Then the processed signal is output to the NET-42 board.
Control signal processor
CPU module (MPU-163B board, MPU-163C board)
The CPU module controls overall boards.
The CPU module has the following main functions.
• FPGA configuration data is stored in the flash memory (IC800). After power is turned on, the CPU module reads
necessary data from the flash memory and performs FPGA configuration.
• Controls FPGA’s peripheral devices (including temperature sensor, EEPROM, and clock device).
• Controls the FPGA.
• Data communication (of recording/updating set values, error report, etc.) with the IP Live System Manager
• Data communication with the upper CPU (on the CA-92 board) through the RS-485 interface
The firmware of the CPU (IC003) processor is stored in the flash memory (IC008), and runs using the SDRAM (IC004
to IC007) as work RAM.
A power voltage of 5 VDC generated in the NET-42 board is supplied. The DC/DC converter (IC002) generates 3.3
VDC from 5 VDC to activate the power control IC (IC001) of the CPU (IC003).
CADEC (IC005)
The CADEC has the following main functions.
• Boot control
After the configuration has been completed, the CADEC releases the CPU module reset to boot the CPU module.
• Monitoring power supply states
• Controls the clock cleaner (IC701, IC702, IC5102)
• Controls the PCIe switch (IC602)
• This CADEC sends/receives commands and status data to/from the upper CPU through the local bus.
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
5-16
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