A series of "1"s and "0"s appears in the chart for each of the 40 channels. A "1" means +DC is applied
to that pin, and a "0" means that pin is grounded. The pin having the highest binary value or
"significance" controls the number of possible channels that can be programmed. In this example the
highest Power-of-2 is "256" at Pin 7, which is called the "Host Significant Bit"; the "Least Significant
Bit" is Pin 15, which is only worth a "1" in binary. A chart like this showing the logic states of each PLL
program pin for each channel is called a "Truth Chart" and is helpful for troubleshooting.
How exactly was the number "330" decided? In Chart you see the truth states for Ch.l only. Above
each PLL program pin are numbers I`ve labelled "P0WERS 0F 2", such as 1, 2, 4, on up to 256 which
is how a binary counter counts. By adding up the weight or significance of every pin showing a "1", the
N-Code is determined. The "0" or grounded pins are always ignored. In this example we have: 256 +
64 + 8 + 2 = 330.
Go back now to Programming Chart and notice how the logic states for Pin 7 and Pin 8 never change
at all for any of the 40 channels. Then look again at Figure 11 and you'll see that those pins are
Dermanently hard-wired such that Pin 7 is always tied to +DC ("1"), ana Pin 8 is always grounded
("0").
You'll often find that many service manuals won't even include these pin states in the Truth Chart
because they never change when programming for the legal 40 channels only. This is a case of those
missing blanks I'm filling in for you, and you can test this idea by checking the rig's schematic.
Compare the total programming pins available to the total number needed for 40 N-Codesl it's an
obvious modification source.
The original 18-channel Australian CB service was legally expanded recently to match the 40 FCC
channels. Hany of the older Aussie rigs, especially those with the Cybernet type PLL02A chassis, are
simply American rigs with a limited Channel Selector switch. These can be easily expanded by
replacing the 18-position switch and wiring up the unused binary bits on the PLL chip.
For example, the original Australian Ch.1 was 27.015 HHz, which corresponds to U.S. Ch.5. The N-
Code here is "325". The N-Code for their old Ch.18 (27-225 HHz) is "304". Reprogramming an old
PLL02A rig for N-Codes greater than "325" or less than "304" expands the channels.
This particular IC, the PLLO2A., has a total of 9 binary programming pins, pins 7-15. So it has what's
called a "9-bit" binary programmer. Some quick math should tell you that the chip has a potential
channel capacity of
2
9 - 1, or 511 channelsl (1+2+4+8+16+32+64+128+256 = 511). 0nly 40 channels
are used for CB purposes but by proper connection and switching of unused pins, many more
frequencies are possible.
The VCO Circuit
Refer back to Figure. This VC0 runs in the 17 MHz range, from 17.180 MHz on Ch.1 to 17.62 MHz on
Ch.40. The VC0 is controlled by an error voltage received from the PD, which is constantly lookingfor
a match at the output of the Reference Divider and Programmable Divider.
The Reference Divider is accurately controlled by a 10.240 MHz crystal oscillator whose signal is
divided down digitally by 1,024 to produce the required 10 kHz channel spacings. If the Programmable
Divider should also happen to output the exact same 10 kHz the result would be perfect; no correction
from the PD, and the loop would be locked.
What would it take to produce a perfect 10 kHz output from the Programmable Divider? We've alredy
seen that the Programmable Divider is set to divide any signal it sees by the number 330. For example
if it should see a signal of exactly 3.30 MHz at its input, the resulting output would be 3.30 MHz + 330
= 10 kHz. So if we can somehow get an input signal of 3.30 MHz, everythirig will fall perfectly into
place.
Loop Mixing
It so happens there's a very easy way to do this by cleverly borrowing a bit of existing circuitry. If some
10.240 MHz energy from the Reference Divider is taken off and passed through a tuned Doubler
stage, the result would be 2 x 10.240 = 20.480 MHz. Here's where that very important loop mixing
principle enters; by mixing the 20.480 MHz signal with the Ch.1 VC0 signal of 17.180 MHz, sum and
difference frequencies are generated. The sum is 20.480 + 17.180 = 37.660 MHz. The difference is
20.480 - 17.180 = 3.30 MHz. Just what's needed to lock the loop. And the 37.660 MHz energy isn't
wasted either; it's used as the high-side mixer injection signal that produces the first- RX IF: 37.660 -
incoming 26.965 = 10.695 MHz IF.
Phase Detector Correction
What happens if the mixing product to the Programmable Divider isn't exactly 3.30 MHz? Let's find
out. Since the N-Code is 330, a signal of other than precisely 3.30 MHz would produce a slightly
different output to the PD. For example a signal of say, 3.10 MHz results in 3.10 MHz + 330 = 9.39393
KHz. The PD will sense this error and try to correct it by applying a DC voltage to the VC0. This
correction voltage will drive the VC0 up or down slightly in frequency, with the PD always comparing
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