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Supermicro X11DAi-N - Page 86

Supermicro X11DAi-N
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
86
Enhanced Halt State (C1E) (Available when Autonomous Core C-State is set to
Disable)

CPU's power consumption by minimizing CPU's clock cycles and reduce voltage during a
"Halt State." The options are Disable and Enable.
Package C State Control (Available when "Power Technology" is set
to Custom)
Package C-State
        
Auto.
CPU T State Control Available when "Power Technology" is set to
Custom)
Software Controlled T-States
If this feature is set to Enable, CPU throttling settings will be supported by the software of
the system. The options are Enable and Disable.
Chipset Conguration
Warning: Setting the wrong values in the following items may cause the system to malfunction.
North Bridge

UPI (Ultra Path Interconnect) Conguration

Number of CPU
Number of Active UPI Link
Current UPI Link Speed
Current UPI Link Frequency
UPI Global MMIO Low Base/Limit
UPI Global MMIO High Base/Limit


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