11
IOW*
MEMR*
MEMW*
FDCDMRQ*
REFRESH*
FDCDACK*
AEN
DMATC
Voltages:
+5Vdc+/-5%,
0
0
0
0
I
0
I
1.4A,
onto the data bus.
It
may
be
driven
by the
processor
or
the DMA controller. This
signal
is
active low.
-I/O Write command: This command line
instructs
an I/O
device
to
read the data
on
the data bus.
It
may
be
driven
by
the
processor
or
the DMA controller. This
signal
is
active low.
Memory Read command: This command line
instructs the memory
to
drive its data onto
the data bus. It may be driven
by
the
processor
or
the DMA controller. This
signal
is
active low.
Memory Write command: This command line
instructs the memory
to
store the data
present
on
the data bus. It may
be
driven
by the processor
or
the DMA controller.
This signal
is
active low.
FDC DMA Request: This line
is an
asynchronous channel request used
by a
floppy disk
to
gain DMA service.
A
request
is generated
by
bringing the line
to an
active level
(high).
The line must
be
held
high until the FDCDACK* line goes active.
-DMA Acknowledge: These lines are
used
to
acknowledge FDC DMA requests and
to
refresh system dynamic memory. They are
active low.
Address Enable: This line
is
used
to
de-gate the processor and other devices
from the
I/O
channel
to
allow DMA transfers
to take place. When this line
is
active
(high),
the DMA controller has control
of
the address bus, data bus, read commnad
lines (memory and I/O), and the write
command lines (memory and I/O).
Terminal Count: This line provides
a
pulse
when the terminal count for any DMA channel
is reached. This signal
is
active high.
located
on 2
connector pins (.45A per
option
board).
.
TANDY COMPUTER PRODUCTS
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