Teac DW-224E-V - Page 22

– 20 –
(Fig. 14.4-7) Ultra DMA transfer timing (Data in burst) (Fig. 1 of 3)
t50
t51
t52
t53
t54
t55
t56
t57
t58
t52
t51
t51
t51
t53
t56
t60
t59
t58 t57
t60
t59
t58 t58
t57
t61
t62
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
–DMACK
(host)
STOP
(host)
−HDMARDY
(host)
H
L
Initiating an Ultra DMA data in burst
DSTROBE
(device)
DD(15:0)
(device)
DA0, DA1, DA2
(host)
H
L
−CS0, −CS1
(host)
H
L
Sustained Ultra DMA data in burst
H
L
H
L
DSTROBE
(device)
DD(15:0)
(device)
Host pausing an Ultra DMA data in burst
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
–
DMACK
(
host)
STOP
(host)
−HDMARDY
(host)
H
L
DSTROBE
(device)
DD(15:0)
(device)