Teac DW-224E-V - Page 23

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(Fig.14.4-7) Ultra DMA transfer timing (Data in burst) (Fig. 2 of 3)
t63
t64
t51
t65
t66
t67
t68 t69
t51
t51
t51
t55
t64 t63
t67
t51
t62
t68
t69
t51
t51
t51
t55
t64
t64
CRC
t64
CRC
t63
t65
Device terminating an Ultra DMA data in burst
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
–DMACK
(host)
STOP
(host)
−HDMARDY
(host)
H
L
DSTROBE
(device)
DD(15:0)
(device)
DA0, DA1, DA2
(host)
H
L
−CS0, −CS1
(host)
H
L
Host terminating an Ultra DMA data in burst
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
–DMACK
(host)
STOP
(host)
−HDMARDY
(host)
H
L
D
STROBE
(device)
DD(15:0)
(device)
D
A0, DA1, DA2
(host)
H
L
−CS0, −CS1
(host)
H
L