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14.4 Interface Timing
The following specifications all apply to the signal interface connector terminal of the CD-ROM drive. In
timing description, H indicates high level (false) and L low level (true).
(1) Reset timing (master/slave) : Fig. 14.4-1
(2) Reset timing (slave) : Fig. 14.4-2
(3) PIO write cycle timing : Fig. 14.4-3
(4) PIO read cycle timing : Fig. 14.4-4
(5) DMA single word transfer timing : Fig. 14.4-5
(6) DMA multi word transfer timing : Fig. 14.4-6
(7) Ultra DMA transfer timing (Data in burst) : Fig. 14.4-7
(8) Ultra DMA transfer timing (Data out burst) : Fig. 14.4-8
DA0 Device address bit 0 IN
DA1 Device address bit 1 IN
DA2 Device address bit 2 IN
–DMACK DMA acknowledge IN
DMARQ DMA request OUT
INTRQ Interupt request OUT
–IOCS16 Drive 16 bit I/O OUT
–IOR
–HDMARDY
HSTROBE
I/O read
DMA ready during Ultra DMA data in bursts
Data strobe during Ultra DMA data out bursts
IN
IN
IN
IORDY
–DDMARDY
DSTROBE
I/O ready
DMA ready during Ultra DMA data out bursts
Data strobe during Ultra DMA data in bursts
OUT
OUT
OUT
–DIOW
STOP
I/O write
Stop during Ultra DMA data bursts
IN
IN
–PDIAG
–CBLID
Passed diagnostics
Cable assembly type identifier
IN/OUT
–
–RESET Reset IN
(Table 14.3-1) IDE Interface signal summary (Sheet 2 of 2)
Signal Description Direction
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