Teac DW-224E-V - Page 26

– 24 –
(Fig.14.4-8) Ultra DMA transfer timing (Data out burst) (Fig. 2 of 3)
t71
t74
t81
t83
t75
t74
t74
t76
t71
t71
t71
t82
t75
t81 t71
t80
t74
t81
t74
t76
t71
t71
CRC
CRC
t71
t82
Host terminating an Ultra DMA data out burst
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
–DMACK
(host)
STOP
(host)
−DDMARDY
(device)
H
L
H
STROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2
(host)
H
L
−CS0, −CS1
(host)
H
L
H
L
H
L
H
L
H
L
H
L
DMARQ
(device)
–DMACK
(host)
STOP
(host)
−
DDMARDY
(device)
H
L
H
STROBE
(
host)
D
D(15:0)
(host)
D
A0, DA1, DA2
(host)
H
L
−CS0, −CS1
(host)
H
L
Device terminating an Ultra DMA data