Teac DW-224E-V - Page 27

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(Fig.14.4-8) Ultra DMA transfer timing (Data out burst) (Fig. 3 of 3)
Symbol Item Min Max Unit
t70 Unlimited interlock time 0 ns
t71 Setup time/Hold time (to –DMACK ↓ )20 ns
t72 Envelope time(–DMACK ↓ to STOP ↓)2070ns
t73 –DDMARDY drive delay time (to –DMACK ↓)0 ns
t74 Limited interlock time 0 150 ns
t75 Data setup time (to –HSTROBE edge/to
–DMACK ↑)
7ns
t76 Data hold time (to HSTORE edge/ to –DMACK ↑)5 ns
t77 HSTORE cycle time Mode 2 54 ns
Mode 1 73 ns
Mode 0 112 ns
t78 HSTROBE x 2-cycle time Mode 2 115 ns
Mode 1 154 ns
Mode 0 230 ns
HSTROBE Average x 2-cycle time Mode 2 120 ns
Mode 1 160 ns
Mode 0 240 ns
t79 Receipt stop shift time (HSTROBE edge
to –DDMARDY ↑)
Mode 2 20 ns
Mode 1 30 ns
Mode 0 50 ns
t80 –DDMARDY ↑ to DMARQ ↓ delay time 100 ns
t81 HSTROBE ↑ to –DMACK ↑ delay time 20 ns
t82 –DDMARDY release time (to –DMACK ↑)20ns
t83 –HSTROBE edge to STOP ↑ delay time 50 ns