Technics SL-PG420A - Page 14

_SL-PGA20A
|
SL-PG420A
* 10401 (MN1871617PMC): System control & FL drive * IC801 (MNG475A): Digital filter & D/A converter BIBLOCK DIAGRAM
lid
0
0
110
em
|
witty
isda
Paton
Division
Division
ids
—
aie
——>
Audio
signal.
[4
|
wo
|
1
|
Power
supply
terminal
TL
Track
loss
input
LIR
discriminating
signal
»
4 -
LRCK
Test terminal {Ordinary: L)
ie:
ee
System
clock
input
(Sb
Reset
terminal
-
Analog
GND
terminal
OPTICAL
PICKUP
UNIT
“SERVO
CIRCUIT
ee
3.
osci
(f=4.2336
MHz)
38
|
SOCK
|
o
|
Sub-code
Q
register
clock
BCLK
Serial
bit
clock
input
i
|
4]
vss
|
|
-
|
GND
terminal
aa
|
sus
|
1
|
Sub-code
0
data
Piel
Mee
ak
|
R
al
ai
Sua
:
2
:
SRTATA
Serlal
data
output
(MSB
first)
Analog
signal
output
(2)
WARE
;
adial
error
digital
signal
5
oN
am
WE
TRAY
SW
Disc
holder
open/close
det.
.
acer]
fs|
xo
|
o
|
terminal:
;
492220972234
ich
Not
Used,
open
4
AVop/R
Analog
power
supply
terminal
(2)
eH0TO
DIODE
Wags
>
IGITAL SIGNAL PROCESSOR
7 | par fot | | ai | aLKck | 1 | Sub-code block clock (=75H2)
| pops IRST 1 [st signal input (Active: L)
STAT
Drop-out detect signal
Status signal
(GRC, CUE, CLVS, TTSTOP,
FCLV, SQOK)
Not used, open
Spindle servo phase synchro
signal
Key return signal
8 P46
is 5
12 P42
rs favor] 0
REG
ENABLE
P37
14
15
SURGUSOCKY NLD SWELK?
exer MpATS
PLETE TTT TTT A tuys STAT TRON SHEK
PWM output (TP---“H”: output,
a] em [oo | Be High impedance)
Synchro rec contro!
<=
g oc
37
4i
42
43
44
Digital power supply termina! fete [| Test terminal (ordinary: L)
i]
i]
t
WVEL poutle velocity {“H”: double,
L”: single)
i]
|
(
|
1
i
[> Leh |
WNGAT5A
5
|
WK
DIGITAL
FILTER
A
roast
erate
8 Reh
SMES
oma
conventeR
eT
Ler
Reb
1
!
fl FFE RE NTL |
AMP
803 404
BASS6ON
HEADPHONES, HEADPHONES
‘AMP [>Lch
LeveL iS HEADPHONES
p> Rb
Fes ~ TY]
FElng Ret 2 TL Pun AD
+ 0 pried
aus he ol
RADIAL DRIVE
Not used, open and connected
to terminal
CLYS
Clock
terminal
(f=33.8688
MHz)
= oC
7
2
1
0
cot 1
TEST
pad
{
H
P34
=
jae
(°H":
CLY,
“L":
Rough
servo}
34
DEMPH
Digitat
de-emphasis
ON/OFF
3
19
|
Poo
|
Tracking
servo
ON
signal
("H";
ON)
‘veaos}20e2)
OBSHE53
671,972
}
TRON ey
20 | a2 | ( V > ON) Digital GND terminal a CSEL red Clock frequency select of DOS Th RAD SiFRD ONS STAT TRH Qs sunwrsacxr wuDywclKs —KuPH DUUeE
; 384 FS terminal
Not
used,
open
and
connected
Radlal
error
digital
signal
=s
24 ft 47 DIV4 we? AEA wNIeTIErTPHe :
es
ae
to
terminal
ow
|
devided
by
four
a
Analog
power
supply
terminal
(1)
384FS
Lo
|
ae
6.9344
MHz)
signal
Ragu
ERROR
SiGNAL
|
“
srsice
“COMTEOL
@
FL
DRIVE
a
!
7
HF /OI~04 GENERATOR
|
PaO
|
|
emer
|
Emphasis
signal
Bek
as
cures
P27 L OUT TeAt SW PAR PAG thon 1G 6 EABBLE REE PRMOON —_oMEHCLOSE TCAosTZOMZR
, 768 fs (33.8688 MHz) signal
PLL on hold input Analog signal output (1) ire eal output (Not used, open)
Not used, connected to GND
Power supply terminal for Fl.
drive :
Not used, open
OPENS
CLOSE
DMUTE
Loading motor control signal
CM
—
2
= a =
a
ae [2jela[s| 3
Muting output (“H”: MUTE) 1 30Hz
0 | On/foff control and ready signal
LOADING
MOTOR
vPP
a o
Contral bits for off-, catch-,
POWER SUPPLY CIRCUIT ' Yer mata
play-status and DAC output
J ici | +439)
current
i
Litzocorsis
pen
TCAOS7Z0NER
gn15, 16 Q35t
56 138G
Po | Remote control signal
Radial error digital signal
+71Y TURNTABLE
' HOTOR
~6ay CONTROL
Blin IT SYNCHRO
I EIT
j#]@{2| es [ele] & |e)
aaa
Ys
a
ee ee
| .
zx
|
|
FL
digit
signal
ta
MDATA Esl Command data signal oe “8s nto
Baa FL OISPLAY
| 34 | MCLK a Command clock signal Pps te } }
Command load signal oe FL segment signal and key scan ! ~80¥
Oo O—-____--» AC.
6
ea
(*L"s
LOAD)
P/SEGP
signal
od
OPERATION
CIRCUIT
LOADING
UNIT
io
RAD
out
:
Current
output
of
integrated
(Re2—Re1)
RE
dig
:
Radial
error
digital.
P42~46
:
Key
return
signal.
LRCK
:
LAR
data
discrimination
clock
(88,.2KHz).
input
currents.
(RE
DIG/X1}
1G~12G
:
FL
digit
signal.
SRDATA
:
Serial
data
output
(MSB
first).
BO~B3
:
Control
bits
for
radial
circult.
RE
lag
:
Radial
error
signal
for
LAG
network.
SEGO~15
:
FL
segment
signal
and
key
scan
signal,
SCK
|
:
Serial
bit
clock
(2.82MHz).
DODS
:
Drop
out
detect
signal.
SRD
:
On/off
control
for
laser
supply
and
focus
MCLK
:
Data
clock
for
MDATA.
(BCLK)
ina
Di~D4
>
Photodiode
currents.
a3
circuit.
SUBQ
:
Sub-cade
Q
data.
MEMP/EMPH
:
De-emphasis
command
(Active
High).
FE
:
Focus
error
signal.
TL
:
Track
loss
signal.
:
CLDCK
:
Data
frame
clock
(7.35
KHz).
SYNC
REC!
_
:
Synchro
rec
control.
FE
lag
;
Focus
error
signal
for
LAG
network.
Diva
:
Radial-error
digital
devided
by
four.
BLKCK
:
Sub-code
Q
data
block
clock
(75
Hz).
REG
ENABLE
HF
out
+
HF
amplifier
and
equalizer
voltage
output.
HFIRF/ARF
:
AF
(Audio)
signal.
SQCK
+
Sub-code
Q
register
clock.
REMOGON
_
:
Remote
control
signal.
HFin
>
HF
current
input.
TRAY
SW
__
:
Disc
holder
open/close
det.
terminal.
RST
:
Reset
command
(Active
Low).
3B4fs/X1,
X2_
:
384
fs
(16.9344MHz)
signal,
LM
:
Laser
monitor
diode
input.
CLVS
:
Spindle
servo
phase
synchro
signal,
TRON
:
Tracking
servo
ON command
(Active
Low).
DEMPH
:
De-emphasis
ON
signal.
@
@
LO
+
Laser
amplifier
current
output.
STAT
;
Status
command
for
CRC
etc.
ECS/IECM
:
Turntable
motor
drive
signal.
LOUT
:
Leh
data
signal.
Re
:
Radial
error
signal
1
(summation
of
DMUTE
:
Data
mute
command.
PC
:
Turntable
motor
ON
command
(Active
Low).
R
OUT
:
Ach
data
signal.
;
,
amplified
currents
D3
and.
D4),
MDATA
:
Mode
control
data.
SMCK
:
System
clock
(4.2336
MHz).
OPEN/CLOSE
:
Loading
motor
contral
signal.
Re2
:
Radial
error
signal
2
(summation
of
MLD
;
Load
command
for
mode
control
data
(OSC1/0SC2)
amplified
currents
D1
and
D2).
(Active
Low).
eee to —fb- a oe | eae: 7 ; a a
' ! has hk 2a eae ili ar aac f Se | a eC ee ye ; h fea: 4 ot or UA es a as