Technics SU-V90D

SU-V90D SU-V90D
m FUNCTIONS OF IC TERMINALS
e1C806 (YM3623B) DIGITAL INTERFACE RECEPTION
(PU) terminals are “pulled up”.
1
VDD1 — This is the power connection terminal (+5 V).
ADJ | This terminal is for the adjustment of the VCO oscillation frequency, but it is not used in this unit.
vco VO This is the external condenser terminal for the VCO circuitry.
4 vss2 _— This is the ground connection terminal of the system.
oO This is the output terminal for the crystal vibrator (16.9344 MHz).
This is the input terminal for the crystal vibrator.
oa] a x | x
(e)
7 KMODE 1 (PU) At a high level...the PLL circuitry is activated when the DIN terminal receives an input signal.
Otherwise, the crystal vibrator is activated.
At a low level...the crystal vibrator is activated, regardless of the DIN terminal input.
8 OA This terminal outputs a 16.9344-MHz frequency when the crystal vibrator functions. When the PLL
circuitry is activated, the frequency varies according to the speed of input data of the DIN terminal
(fs=about 16.9344 MHz when it is 44.2 kHz).
9 2B The frequency of this terminal is divided into a third of that of terminal @A when the crystal vibrator
functions. When the PLL circuitry is activated, the frequency varies according to the speed of input data
of the DIN terminal (fs=about 16.9344 when it is 44.2 kHz).
At a high level...data on the left channel is output from the DO terminal.
At a low level...data on the right channel is output from the DO terminal.
_
oO
= —
r
BCO
13 SYNC
_
Le)
14 vssi
i
Be)
= re)
DEF Ata high level...input data is emphasized.
At a low level...input data is not emphasized.
Outputs 16-bit data
NX
foo)
DIGR
= —_
a
20 DIGL
nN Nh
SEL 1 (PU)
a
nN
o wn
—
Terminal for the clock-signal of the sub code output.
SCK
SSYNC
For the signal of the sub code
For the output of sub code data
| (PU) For the input of data.
NX
—~33—
Terminal
Name
e YM3404B (Digital filter)
ee Mark v0 Function ph Mark iffe) Function
1DAC(ST ="L”): Lch Deglitcher signal
1DAC(ST ="L”): L/Rch data output terminal
BLO 2 2DAC(ST =H”): Lch data output terminal
1 {| SHL | © |opac(st="H"): L/Rch Deglitcher signal
2 xo | o
Clock output
3 x1 | Clock input
Rch data output (not connected)
Output data word clock
VDD2 | | Power supply (connected to +5V)
12 Bit clock output (output data)
5 BCI | | Bit clock input (input data) 13 GND terminal =a
6 SDSY ! R/L signal 14 1DAC/2DAC selector terminal
7 SDI | | Data input 15 System clock selector terminal
8 vbpD1 | | Power supply (connected to +5V) | 16 | sir 1DAC(SP ="L”): Rch deglitch signal i
e MN53010PEH (Serial/Parallel converter)
vo Function
re) Output data word clock
(DALO,DBLO,DARO,DBRO)
{———____
Rch data output, (+)terminal
fe)
O | Rch data output, (-)terminal
fe)
Reset output data to “0”
| Power supply (connected to +5V)
im
6 vss | GND terminal
“H”: 2DAC 18-bit
“L”: 2DAC 17-bit
“H”: ADAC 18-bit
“L”: 4DAC 17-bit
“H”: Phase inversion
2 PHASE “L’: Normal mode
+—
10 [ LRCK | | Inverter input
LRCK signal inverter output
Data input
Input data word clock
| Input data bit clock
GND terminal!
Not connected
Power supply (connected to + 5V)
Rch Deglitcher signal
Pin
No. | Mark VO Function
18 | SHR | | Rch Deglitcher signal
Lch Deglitcher signal
Not connected
NORMAL
MODE
delay:
180ms
delay:
NTEST1
“XH”: Normal mode
"L”: Reset
NTEST3
DALO O | Lch data output, (+)terminal
36 DBLO O | Rch data output, (-)terminal
37 VDD I Power supply (connected to + 5V)
38 vss | | GND terminal
Not connected
Gain selector signal H: 0~-12dB
L: below -12dB
Deglitch signal H: Sample
L: Hold
Output data bit clock
~34—