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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
INTENSITY is an input to the Z-Axis/RF Interface board
to control trace brightness.
PEAK/AVERAGE is a digital storage input that causes
signals to be peak detected above, and averaged below, a
display line that tracks this control.
MANUAL SCAN varies the horizontal position of the
sweep in manual sweep mode.
POSITION centers the sweep and vertical deflection on
the crt.
LOG CAL varies the video signal level prior to the Video
Processor board.
PEAKING controls front-end response of the analyzer by
fine-tuning the internal preselector or varying the bias of an
external mixer.
AMPL CAL adjusts 10 MHz IF gain.
ACCESSORIES INTERFACE BOARD
£
The Accessories Interface board provides access to the
instrument bus and connection for two analog signals. The
instrument bus access may be used for diagnostics; it may
also be used by future accessories.
The analog signals are an input, EXT VID IN, and an
output, EXT PRESEL. To display an external signal applied
to EXT VID IN, place a TTL low on EXT VID SEL. EXT
PRESEL can drive an external preselector for use with an
external mixer; it is available only with Option 01 and is valid
only in preselector bands (1.7 GHz to 21 GHz). This signal
tracks the instantaneous frequency at a nominal
2.1 GHz/volt with zero output corresponding to 2.072 GHz.
The instrument bus is buffered and brought out to the
rear panel with the lines named to indicate their relation to
the internal bus: ADV for DATA VALID, APOLL for POLL,
etc.
Two lines are added to define the 492/external device
interface. One, INTL CONT, is asserted low by an external
controller to disable the internal microcomputer’s instrument
bus buffers. This sets the address lines buffer, U2033, and
control lines buffer, U2015, to drive the address, DATA
VALID and POLL lines, and listen to SER REQ. It also sets
U2038 to indicate the direction of data through the data
lines buffer, U2025, depending on the sense of the MSB of
the address—AB7. When INTL CONT is low, it sets U2038
to drive the buffer in a manner similar to the Processor
board data buffer—a write to the internal bus if AB7 is low
and a read if AB7 is high. When INTL CONT is high, the
buffer is enabled to write to the external bus when AB7 is
low and read when AB7 is high.
The other line is asserted low by an external device to
enable the data buffer. As long as this line, DATA BUS EN
ABLE, is unasserted, the data buffer is set to its high-imped
ance state and the data direction input has no effect on its
output.
POWER SUPPLY
The Main Power Supply furnishes all the regulated
voltages for the 492/492P, except for the crt high-voltage
supply. In order to reduce total weight and conserve energy,
the Main Power Supply is of the high-efficiency design. The
power supply consists of the line input circuit, which rectifies
and filters the incoming line voltage; the inverter, which
drives the primary of the power transformer; the rectifier-
filter circuit, which rectifies and filters the secondary
voltages; the voltage reference circuit, which furnishes a
stable and precise reference for the regulators; the regulator
circuts, which control the voltage and current for the sup
plies that requires precise regulation.
The Fan Driver board houses the Fan Driver circuit,
which furnishes the appropriate drive current for the fan mo
tor. It also contains the Overvoltage Protection circuit,
which shuts down the +5 V supply in case of overvoltage.
Refer to Diagram 43.
MAIN POWER SUPPLY <A$
Line Input Circuits
Power is applied through the line filter FL301, then
through the line fuse and additional normal mode/common
mode EMI filtering to the power switch, from where it is sent
through line selector connector J1091. The line filter pre
vents power line interference from entering the power sup
ply and internally generated signals from radiating out the
power cord.
Line selector connector J1091 permits the instrument to
operate from either 115V nominal or 230 V nominal line
REV AUG 1981
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