Tektronix 492 - Page 264

Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Table 5-26
GPIA REGISTERS
Register
Type
RS2 RS1
RSO
DBIN
& WE
Interrupt Status 0
Read
0 0
0
1
Interrupt Mask 0
Write
0 0
0
0
Interrupt Status 1
Read 0 0 1
1
Interrupt Mask 1
Write
0 0 1
0
Address Status
Read
0
1
0
1
Bus Status
Read 0
1
1
1
Auxiliary Command
Write 0
1
1
0
Address Switch
Read
1
0 0
1
Address
Write
1
0 0
0
Serial Poll
Write
1 0 1 0
Command Pass Through
Read
1 1
0
1
Parallel Poll
Write
1 1
0
0
Data In
Read
1 1
1
1
Data Out
Write
1 1 1 0
The bus management buffers in U1011 are automatically
configured by TE and ATN to operate in the required direc
tion (driving DAV and EOI when TE is high and NDAC and
NFRD when TE is low).