Product: 492 Ser.1
Date: 2-12-85 Change Ref: M55287
Each side of the converter has two DAC's summed together to produce
an output of approximately +/- 10V. The DAC's are programmable
current generators driving the preamplifier-integrator circuit.
The high-order DAC provides 0 - 2 ma of current to the circuit via
the buffer, while the low-order DAC provides approximately +/- 2.5 mV
at the inverting input of the preamplifier. The preamplifier then
drives the integrator via the storage gate.
Since the converters provide the DC voltages to tune the oscillators in
the instrument, moise and extraneous signal susceptibility must be kept
to a minimum, hence the isolated ground system for each half of the
circuit.
Track/Hold Amplifier
The amplifier consists of high-order DAC U2060, low-order DAC U2055,
buffer U2050, preamplifier U1065, storage gate FET Q1065, and
integrator U2070.
The circuit output is required to tune approximately +/- 10V for the
full-scale range of U2060. When U2060 is off and U2050's output is
at OV, the +10V output level is set by the 1 ma of current in R1055,
and the combination of R1032, R1053, and R1070. When U2060 is fully
on, and U2050's output is at +10V, the -10V output level is set by
the 2 ma of current in R1052, minus the 1 ma constantly flowing in
R1055. Full-scale gain is adjusted by R1032. R1052, R1053, and
R1055 are TC matched to minimize output voltage drift as a function
of temperature. Low-order DAC U2055 tunes approximately +/- 2.5mV
at pin 1, and its gain is adjusted by RIO28. The gain of preamplifier
U1065 is set at about 10,000 by R1056 and the 5 Ohm combination of
R2059 and R2060. The combination of CR1056, CR1058, R1054, and
R1059 limits the gain of U1065 when the output exceeds approximately
0.7V in either direction.
U1065 is connected to integrator U2070 via storage gate FET Q1065,
which is on in the Track mode. Q1065 is turned off any time one of
the DAC's is being tuned to allow its output to settle before tuning
U2070's output. It is also turned off during the interval when a
carry from the low-order DAC to the high-order DAC is being
accomplished. Q1065 is controlled by Q1061. When Q1061 is on,
CR1064 is back-biased. The voltage at the gate of Q1065, which is
developed by R1064, R1065, R1066, and R1067, is near 0V and Q1065
conducts. When Q1061 is off, sufficient voltage to pinch off Q1065
is applied through R1062 and CR1064.
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