Tektronix 576 - Step Generator Circuit Details

Circuit Descri p tion-Type 576
Step
Generator
The p ur p ose of the step generator is to p resent α d iscrete
level of current or voltage to t he base or emitter (or eq uiva-
lent terminals)
of t
h
e d evice under
test for
eac
h
swee p , or
ch ange of d irection of swee p , of t h e collector supp ly . T
h
ese
d iscrete levels are generated in t h e form of ascen d
ing
ste p
s
w
h
ic
h have α calibrated curren t or voltage se p aration .
T he ste p generator circuit consists of four ma j or sec-
tions : t h e cloc k , t h e cou n ter, t he
d igital-to-analog con-
verter, and t h e pulsed ste p s o p eration section . T
h
e cloc k
circuit pro duces negative-going cloc k p ulses w h ic h d eter-
mine t h e rate and ph ase, with res p ect to t h e collector sup -
p ly, of t h e Step Generator out p ut . T he counter circuit
cou n ts t h ese cloc k p ulses an d transforms each count into α
d igital co d e w h ic h controls t he d igital-to-analog converter .
T he d igital-to-analog converter transforms t he d igital co d e
into analog current w h ic h is summe d at α current summing
no d e and transmitted to t he ste p am p lifier . T he p ulsed
ste p s op eration circuit p rovi d es
α variatio n
of t he Ste p Gen-
erator outp u t w h ere s h ort duration p ulse d ste p s rat h er t han
normal ste p s are generate d .
L ogic . T he cloc k circuit, the counter circuit an d α por-
tion of t he digital-to-analog circuit are d igital circuits w h ic h
m
a ke use of tra
n
sistors a nd i n tegrate d circuits in d igital
configurations . T he most convenient met h o d of d escribi n g
and un d erstanding digital circuitry is t h roug h α logic
description rat
h
er t h an α d etaile d
circuit
descri p tion . In
ord er to ma k e t h is d escri p tion und erstan d able by α wid er
range of rea d ers, α sim p lifie d logic d escri p tion, using hig h
and low rat h er t han true an d false, h as been utilize d . Α
k nowle dge of basic logic symbols ( N A ND gates, NOR gates,
fli p -flo p s, etc .)
and
tr u t h
tables
will h elp in
u
nd erstan d ing
t h is descri p tion .
Sim p lified sc h ematics of t h ese circuits are s h own in F igs .
3-4, 3-5 an d 3-6 . Also inclu de d in t h ese figures are trut h
tables and some internal logic d iagrams for t he logic devices
u se d . P ertinent logic level information for t hese logic d e-
vices is s h own in blue on t he Step Generator sc h ematic .
F amiliarity wit h th e logic symbols and relate d trut h tables
of t h ese logic d evices will greatly ai d in un d erstanding t he
following d escri p tion . t
Cloc k . Sine waves p ro duced at line fre q uency by trans-
former Τ 701 p rovi de t h e timing source for t he clock (see
t h e Ste p Generator sch ematic) . Transformer Τ
701,
steering
diodes D1-D2 and D10-D11, an d trigger generators
U 3A- U3 B and U 3C- U 3D o p erate together to pro d uce low
level p ulses at t he in p uts of U 22A . U sing U 3A- U3 B as an
1 Th e sc h ematics and b loc k diagrams in t h is m anual w hi ch i nvo l ve
digital logic are drawn in te r ms o f negative logic . In negative logic,
t he true state is t he m o r e negative of t he two logic levels and t he
f alse state
is t h
e
m o r e p osit i ve . Th e small circles on some o f t he
in p ut o r o u t p ut te r mina
l
s o
f
th e
logic sy m bols indicate α logic nega-
tion . Any te r minal h aving
α
logic
negation symbol on it will be at a
f alse level w hen t h e re l ated device is in its activated state . F o r
further in
f
o rm atio
n
see U SA
Standa r d Υ 32 .14 1962 .
3- 6
exam p le, each time the transformer voltage at the ano d e of
D1 crosses zero going negative, D1 will turn off an d D2 will
turn on . Wh en D2 is con d ucting, t h e voltage at t he pin 1
in put of U 3A is h eld at α low voltage level . Since t he other
in put
to U
3A, p in 2, is h el d at α h ig h voltage level by
voltage d ivi d er R 4- R 5, t h is low causes α h ig h to a pp ear at
t he out p ut of U 3A (see trut h table for N O R gate s h own in
F ig . 3-4) . T h is h ig h is inverte d by U3 B an d th e resulting low
is a pp lie d to t he p in 1 in put of U 22A . T h is low out put
p ro d uce d by t h e trigger generation continues until C5
ch arges to α h ig h voltage level as d etermine d by d ivi d er
R 4- R 5 . Wh en t he voltage at D1 crosses t h roug h zero going
positive, D1 tur n s on and D2 t u rns off . W it h D2 off, both
in puts to U3A are h ig h , t h e out p ut goes low an d th e out put
of U3 B goes h ig h . T h is is t he quiescent state of t h e trigger
generator . Trigger generator U 3D- U3C op erates t h e same as
U3 B - U 3A exce p t t h at t he a dd itional in put at p in 9 of U3C
allows t he trigger ge nerator to be in h ibite d w h en α low is
a p p lied to it .
Since Transformer Τ 701 (see F ig . 3-4) is center ta pp ed,
t h e voltages at its out p uts are e q ual and o pp osite . Since t h e
two trigger generators are triggere d by Τ 701, th ey o p erate
i n o pp osite ph ase, pro d ucing alternate low level p ulses at
t h eir out puts . Since Τ 701 is in phase with th e Collector
Su pp ly outp ut, α p ulse is generate d by one of t h e trigger
generators at t h e start of eac h collector swee p (assuming
+
ΝΡΝ or -
ΡΝΡ p
olarity) .
Z
ER O CR OSS a
d j ustme n t R 8
allows a d j ustment
of trigger level of
trigger
gen erators .
W it h t h e N ORM R AT E bu tton presse d , low p ulses from
t he trigger generator are inverted to U 22A and transmitted
to norm p ulse gate U 22 B . T he p in 5 in put to U 22 B is
n ormally h el d h ig h . Α h ig h at its oth er in p ut, t h erefore,
p roduces α low at its out p ut . T h is low is app lie d to U 22C,
w h ic h produces α h ig h level cloc k p ulse to be a pp lie d to t he
co
u
nter
circuit . W it h t he N
O
RM R AT
E butto
n p
resse
d , t he
rate of production of clock p ulses (an d th erefore t h e ste p
generator rate) is 120 p ulses/secon d (assumi n g α 60 H z line
fre q uency) w h ic h is t he normal collector su pp ly rate .
H ig h level out put p
ulses from
U
22A are also a pp lie d to
t he base of Q23 (s h own on t he Step Generator sc hematic),
t he in p ut to t h e d elay
circuit . T h is circuit generates cloc k
pulses at t he
normal rate, but d elaye d (wit h respect to t he
start of each normal cloc k p ulse) by α d
elay time eq ual to
h alf t he time
duration between normal cloc k p ulses . T h is
d elay circuit
is triggere d each time α h ig h is p ro d uce d at t he
out p ut of U 22A . T h is h
ig
h
turns
on
Q23, an d p ulls d own
on t h e base of
Q30, t u rning it off . Si nce Q23 is pulling
d own on one
si d
e of
C26, t h e oth er side begins ch arging . It
continues to c
h
arge
until α h ig h enoug h voltage is reac he d
to again turn on
Q30 . Wh en Q30 turns
on,
α
low
level is
p
ro duced
at its collector, w h ic h is d ifferentiated by C33
an d R33 i
n
to α
negative-going s p i k
e a
n
d
app lie d to t he
i np ut of i n verter U 33A . T h e result of t h is low at t
h
e
in put
of U 33A is α h ig h at its out p ut, and t hus α h
ig
h -level d
e-
laye d p ulse at t he p in 13 in put of U 22D . T h e d elay time of
t he h alf-step d
elay circuit is controlled by D EL AY ad j ust-