Tektronix 576 - Page 49

Circuit Descri p tio n
-Ty p
e 576
ment R 24, w h ic h co n trols t hec
h arge ti r ne of C26 . R 24 is
a d j uste d for α d elay time e q ual to h alf t h
e
d uration of
α
normal ste p (about 4167μ s) . Delaye d cloc k p ulses, t h ere-
fore, occur coinci d ent with t he p ea k of t h e Collector
Su
pp ly out put . S W 27 lengt hens t h e d elay time of t h is
cir-
cuit to 5000μ s w hen Τ 701 is op erate d with α 50H
z
li n
e
fre q uency .
T
h
e cloc k
circuit has two sources of cloc k p ulses, t he
output
of U 22A and t he out p ut of t he delay circuit . T
h
e
various ste p generator rates are pro d uce d by in h ibiting
some of
t h e clock p ulses from t h ese two sources from being
summe d by U22C . T h ree d evices control t he transmission
of
cloc k p ulses t h roug h t he circuit : Trig Gen Gate U 20C,
Norm
Pulse
Gate
U 22 B and Delaye d Pulse Gate U 22D .
Wh
en
t he N O RM R AT E button is p resse d , p in 9 of U3C
is h el d
h ig h , enabling trigger generator U 3D- U 3C . Α h ig h is
also a pp
lie d to pin 5 of U 22 B , allowing t he cloc k p ulses
from U 22A to be transmitte
d
to p
in 9 of U22C . Α low is
applied to p in 12 of U 22D,
in h ibiting t h
e
delayed cloc k
p ulse . Wh en t he .5 ΧRAT E button
is p resse d , t he circuit
operates as d escribe d for normal o p
eration
exce p
t t h at bot h
in p uts of U20C are hel d h ig h , w
h
ic
h h
ol d
s p in 9 of
U
3C
low an d in h ibits trigger generator U 3C- U3D . T
h
e
result is α
step generator rate of half t h e normal rate, 60 ste p
s/secon
d
(ass u ming α 60 H z line fre q uency) . Pressing t h e 2Χ RAT E
b utton
causes normal o p eration of t h e circuit, exce p t t h at α
hig h is a pp lie d to p in 12 of U 22D, allowing t he delayed
cloc k pulses to be app lie d to p in 10 of U22C . T h e ste p
generator rate in t h is case is 240 ste p s/second . Wh en bot h
th e 2 Χ RAT E an d t h e .5 Χ RAT E buttons are p resse d , t he
nor m al cloc k p ulses are in h ibite d by α low at p in 5 of U22B
and t h e d elayed clock p ulses are transmitted to U
22C
. In
t h is case t he Step Generator rate is
normal, but t he ste
p
s
occur out of
ph
ase
with t h
e
normal ste p s by t h e delay time
of t h e d
elay circuit .
Counter . Wh en
t h
e
cloc k circuit generates α cloc k p ulse,
it is counte d by t h e counter (see F ig . 3-5) .
T h
e counter
counts cloc k p ulses until it reac h es α p reset number, t h en
resets and begins counting again . E ach time t he counter
counts,
it c h anges
α
four-bit binary code w h ic h is a pp lie d to
t he
digital-to-analog converter .
U 70 is α d ivi d e-by-16 counter
with t h e out puts of all
four of
its internal fli p -flo p s utilize d (see Fig . 3-5) . Α nega-
tive p ulse at
t h e p in 14 in put of U70 causes α count to be
recor d e d
by t he fli p -flo p s . In record ing α count, t he fli p -
flo p
s assume h ig h or low states accor d ing to α 1-2-4-8
binary co
de . Α h ig h state re p resents t h e p resents of eit her α
1, 2,
4
or
8 . Α
low
state re p resents α 0 . Out put terminals
12, 9, 8 and
11
of U
70 re p resent 1, 2, 4 an d 8 res p ectively .
By connecting p
in
8 an
d p in 11 of U70 to U 72D t h roug h
inverters,
t h
e
1-2-4-8 co d e of t he U 70 out puts is mo d ifie d
to α 1-2-4-4 code . T he trut h table in Table 3-1 s h ows t he
state of each mo d ifie d
counter
out
put for successive counts
counte d by U70up to 11 . Wh enever U
70 is reset, it returns
to
t h
e
zero count state wit h lows
on
all t he outputs .
3- 8
TA BLE 3-1
N ormal and
M
o d ified Cou
n ter O ut pu t Codes
T h e counter may be reset after from 1
to 10 ste p s
h
ave
been prod uce d . T he NUMBER
O
F
ST
EP
S switc h d eter-
mines on w h ic h cloc k p ulse t he counter is reset . T
h
is switc
h
p resets t he in puts to U 75, so t h at w hen t he counter h as
counte d t he desire d number of clock p ulses, α h ig h is gener-
ated at p ins 2 an d 3 of U 70, resetting t he counter . T h is
h
ig
h
is obtaine d from α h ig h at t h e out p ut of reset trigger genera-
tor U 75 . U75 consists of four 2-in p ut O R gates w hose out-
p uts are connected to α 4-in p ut N A ND gate . One in put of
each O R gate is connecte d t h roug h an inverter to an out put
of t he modifie d counter . T he oth er in put is connecte d to α
section of t he NUMBER O F STEP S switch . Wh en α low
a pp ears on one in put of each O R gate of U 75, all four
in p uts to t h e U 75N A ND gate will be low an d α h ig h reset
p ulse is prod uce d at t he out put . T
h
is con d ition of h
aving
at
least one low on
eac h
O
R gate of U75 is ty p ically obtaine d
by first setting lows onsome of t h e OR gates t h roug h t he
NUMBER O F STEP S switch . T h e counter t h en cou nts until
lows are prod uce d by t he mo d ifie d counter out p ut at t he
OR gates with out p reset lows . Wh en no p reset lows are
app lie d to U 75, t he counter is reset w h en it reach es t he
elevent
h
step (1 + 2 + 4 + 4 = 11) w hen α 11 mo d ifie d
counter out p uts are low . It s hould be note d t h at t he cloc k
p ulse
w h ic h causes t he counter to be reset is always one
cloc k
Pulse
more t h an t h e n umber selecte d by t h e NUM-
BER
O
F ST EP S switc h . T h e time duration from t he point
at w h ic h t h is extra cloc k p u lse is counte d by t h e counter to
t he p oint w hen t he counter is reset is so s h ort t h at t he extra
ste p never appears at t h e Ste p Generator outpu t-
T h e h ig h at t h e out p ut of U75 is i nverted by U 33 B (see
t he Step Generator Sc h ematic) and again by U 69C, pro-
d ucing α reset h ig h at p in 2 and 3 of U 70 . U
71
D
and C81
stretc h t he reset h ig h to α long-e n oug h duration to assure
t h at t he counter is reset .
Cou n t N ormal Co de
M
odifie
d
Co
d
e
P ins on U 70
P i
n
s
on
U 70 U 72D
12 9 8 11 12 9
11 11
0 L L L L
L L L L
1 Η L L L
Η L L L
2 L Η L L
L Η L L
3 Η
Η L L Η Η L L
4 L
L Η L L L Η L
5 Η L
Η L Η L Η L
6 L
Η Η L L Η Η L
7 Η
Η Η L Η Η Η L
8 L L L
Η L L Η Η
9 Η L
L Η Η L Η Η
10 L Η L
Η L Η Η Η
11 Η Η L Η
Η Η Η Η