Tektronix TDS Series - Page 373

Appendix D: Factory Initialization Settings
D–4
TDS Family Oscilloscope Programmer Manual
Table D–1: Factory Initialization Settings (Cont.)
Control Changed by Factory Init to
Logic trigger class TDS 500B, 600B, & 700A: Pattern
Logic trigger input
(pattern and state)
TDS 510A, 500B, 600B, & 700A:
Channel 1 = H (high),
Channels 2 & 3 (Ax1) = X (do not care)
Logic trigger logic
(pattern and state)
TDS 510A, 500B, 600B, & 700A: AND
Logic trigger pattern time qualification
Lower limit
Upper limit
TDS 510A, 500B, 600B, & 700A:
5 ns
5 ns
Logic trigger Setup/Hold times
Setup
Hold
TDS 500B, 600B & 700A: 3 ns
TDS 500B, 600B & 700A: 2 ns
Logic trigger sources and levels
(Setup/Hold)
TDS 500B, 600B & 700A:
Data Source = Channel 1 = 1.4 V
Clock Source = Channel 2 = 1.4 V
(Source levels are clipped to 1.2 V at the
default volts/division setting established by
Factory Init)
Clock Edge = Rising
Logic trigger threshold (all channels) (pattern
and state)
TDS 510A, 500B, 600B & 700A: 1.4 V
(clipped to 1.2 V at the default volts/division
setting when no 10X probe attached)
Logic trigger triggers when ...
(pattern and state)
TDS 510A, 500B, 600B & 700A:
Goes TRUE
Main trigger mode Auto
Main trigger type Edge
Math1 definition Ch 1 + Ch 2
Math1 extended processing TDS 510A, 500B, 600B & 700A:
No extended processing
Math2 definition Ch 1 – Ch 2 (FFT of Ch 1 for instruments with
Option 2F Advanced DSP Math)
Math2 extended processing TDS 510A, 500B, 600B & 700A:
No extended processing
Math3 definition Inv of Ch 1
Math3 extended processing TDS 510A, 500B, 600B & 700A:
No extended processing
Measure delay edges Both rising and forward searching
Measure delay to Channel 1 (Ch1)