LM940 Hardware Design Guide
1VV0301352 Rev. 18 Page 32 of 75 2022-01-04
6. DIGITAL SECTION
Logic Levels
Unless otherwise specified, all the interface circuits of the LM940 are 1.8V CMOS logic.
Only USIM interfaces are capable of dual voltage I/O.
The following tables show the logic level specifications used in the LM940 interface
circuits. The data specified in the tables below is valid throughout all drive strengths and
the entire temperature ranges.
Warning: Do not connect LM940’s digital logic signal directly to
OEM’s digital logic signal with a level higher than 2.3V for 1.8V CMOS
signals.
6.1.1. 1.8V Pins – Absolute Maximum Ratings
Absolute Maximum Ratings – Not Functional
Input level on any digital pin when on
Input voltage on analog pins when on
Table 21: Absolute Maximum Ratings – 1.8V Pins
6.1.2. 1.8V Standard GPIOs
Low-level input
leakage current
High-level input
leakage current
Low-level input
leakage current
High-level input
leakage current
Table 22: Operating Range – Interface Levels (1.8V CMOS)
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