Texas Instruments MSP430x1xx - Page 309

USART Registers: SPI Mode
14-18
USART Peripheral Interface, SPI Mode
UxRXBUF, USART Receive Buffer Register
76543210
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
r r r r r r r r
UxRXBUFx
Bits
7−0
The receive-data buffer is user accessible and contains the last received
character from the receive shift register. Reading UxRXBUF resets the OE
bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and
the MSB is always reset.
UxTXBUF, USART Transmit Buffer Register
76543210
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
rw rw rw rw rw rw rw rw
UxTXBUFx
Bits
7−0
The transmit data buffer is user accessible and contains current data to be
transmitted. When seven-bit character-length is used, the data should be
MSB justified before being moved into UxTXBUF. Data is transmitted MSB
first. Writing to UxTXBUF clears UTXIFGx.