I
2
C Module Registers
15-23
USART Peripheral Interface, I
2
C Mode
I2CDCTL, I
2
C Data Control Register
76543210
Unused Unused I2CBUSY
I2C
SCLLOW
I2CSBD I2CTXUDF I2CRXOVR I2CBB
r0 r0 r−0 r−0 r−0 r−0 r−0 r−0
Unused
Bits
7−6
Unused. Always read as 0.
I2CBUSY
Bit 5 I
2
C busy
0I
2
C module is idle
1I
2
C module is not idle
I2C
SCLLOW
Bit 4 I
2
C SCL low. This bit indicates if a slave is holding the SCL line low while the
MSP430 is the master and is unused in slave mode.
0 SCL is not being held low
1 SCL is being held low
I2CSBD
Bit 3 I
2
C single byte data. This bit indicates if the receive register I2CDRW holds
a word or a byte. I2CSBD is valid only when I2CWORD = 1.
0 A complete word was received
1 Only the lower byte in I2CDR is valid
I2CTXUDF
Bit 2 I
2
C transmit underflow
0 No underflow occurred
1 Transmit underflow occurred
I2CRXOVR
Bit 1 I
2
C receive overrun
0 No receive overrun occurred
1 Receiver overrun occurred
I2CBB
Bit 0 I
2
C bus busy bit. A START condition sets I2CBB to 1. I2CBB is reset by a
STOP condition or when I2CEN=0.
0I
2
C bus not busy
1I
2
C bus busy
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