ADC12 Registers
17-22
ADC12
MSC
Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.
0 The sampling timer requires a rising edge of the SHI signal to trigger
each sample-and-conversion.
1 The first rising edge of the SHI signal triggers the sampling timer, but
further sample-and-conversions are performed automatically as soon
as the prior conversion is completed.
REF2_5V
Bit 6 Reference generator voltage. REFON must also be set.
0 1.5 V
1 2.5 V
REFON
Bit 5 Reference generator on
0 Reference off
1 Reference on
ADC12ON
Bit 4 ADC12 on
0 ADC12 off
1 ADC12 on
ADC12OVIE
Bit 3 ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to
enable the interrupt.
0 Overflow interrupt disabled
1 Overflow interrupt enabled
ADC12
TOVIE
Bit 2 ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be
set to enable the interrupt.
0 Conversion time overflow interrupt disabled
1 Conversion time overflow interrupt enabled
ENC
Bit 1 Enable conversion
0 ADC12 disabled
1 ADC12 enabled
ADC12SC
Bit 0 Start conversion. Software-controlled sample-and-conversion start.
ADC12SC and ENC may be set together with one instruction. ADC12SC is
reset automatically.
0 No sample-and-conversion-start
1 Start sample-and-conversion
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