Instruction Set
3-24
RISC 16−Bit CPU
AND[.W] Source AND destination
AND.B Source AND destination
Syntax AND src,dst or AND.W src,dst
AND.B src,dst
Operation src .AND. dst −> dst
Description The source operand and the destination operand are logically ANDed. The
result is placed into the destination.
Status Bits N: Set if result MSB is set, reset if not set
Z: Set if result is zero, reset otherwise
C: Set if result is not zero, reset otherwise ( = .NOT. Zero)
V: Reset
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Example The bits set in R5 are used as a mask (#0AA55h) for the word addressed by
TOM. If the result is zero, a branch is taken to label TONI.
MOV #0AA55h,R5 ; Load mask into register R5
AND R5,TOM ; mask word addressed by TOM with R5
JZ TONI ;
...... ; Result is not zero
;
;
;or
;
;
AND #0AA55h,TOM
JZ TONI
Example The bits of mask #0A5h are logically ANDed with the low byte TOM. If the result
is zero, a branch is taken to label TONI.
AND.B #0A5h,TOM ; mask Lowbyte TOM with 0A5h
JZ TONI ;
...... ; Result is not zero
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