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THOMSON VTCD 200 - Page 10

THOMSON VTCD 200
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ITAL
-
SCHALTBILD
DIGITALVERARBEITUNG
-
SCHEMA
ELABORAZIONE
DIGITALE
-
a
2SA1015
E
<
)
2
U1
100uH
D
C7
:
.0033uF
(M)
c
C6:
.0033uF(M)
.
E
cit
0.01M
E
Cl
TA2Z065F
470P
pf
pe
|
4
K
R
3
KR
ZU
KL
vd
se
ia)
2
ae
ett
47k
a
oe
eee
GNO1
LI
QUT(+
PVCCt
ouT(-)1
PW_
g18
+585
vn
C48
3
P
220uF
:
C39
=
sili
[toate
oart+t+]
CONS
ee
a
4558
N
=|
Saess4,en
14
ABBREVIATIONS
-
ABREVIATIONS
-
ABKURZUNGEN
-
ABREVIAZIONI
-
ABREVIACION
AFOK
AIN1
AOUT1
ASW
ASY
ASYI
ASYO
ATSC
BCK
BCKI
BIAS
C.OUT
C210
C2PO
C4M
CB
CC1
CC2
CLK
CLKO
CLTV
CNIN
CP
DATA
DATO
DEEMP
DIG
DM
DOTX
E
EFM
EMPHI
EXCK
F
FZC
FA
FDFCT
FE
FE-M
FE-O
FEB
FEED
FEI
FEO
FE_Bias
FF
FGD
FIL
FILO
FLB
FO
FOK
FOK
FR
FSET
FSR
GFS
GTPO
ISET
When
focus
is
OK
on
first
search
Left-channe!
operational
amplifier
input.
Left-channel
analog
output.
Slice
level
Slice
level
of
EFM
signal
Asymmetry
comparator
voltage
input.
EFM
full-swing
output
(low
=
Vss,
high
=
Vdd).
Window
comparator
input
for
ATSC
detection.
D/A
interface.
Bit
clock
output.
D/A
interface.
Bit
clock
intput.
Constant
current
input
of
the
asymmetry
circuit.
Track
number
count
signal
output.
Bit
clock
output
4,2336
MHz
/
2,1168
MHz
C2PO
output.
4.2336MHz
output.
1/4
frequency-divided
VCKI
output
in
CAV-W
mode
Connects
the
defect
bottom
hold
capacitor.
Defect
bottom
hold
output.
Connected
internally
to
the
interruption
comparator
input.
Input
for
the
defect
bottom
hold
output
with
capa-
citance
coupled.
Serial
data
transfer
clock
input
from
CPU.
(no
pull-
up
resistance)
Serial
data
transfer
clock
output.
Master
VCO
control
voltage
input.
Track
jump
count
signal
input.
Connects
the
MIRR
hold
capacitor.
MIRR
compa-
rator
non-inverted
input.
Serial
data
input
CPU.
(no
pull-up
resistance)
Serial
data
ouput
Deemphasis
Dig
output
for
LED.
Disc
motor
Digital
output
Connects
these
pins
to
photo
diodes
F
and
E.
F
!-
V
and
E
I-V
amplifier
inverted
input.
HF
signal
to
decoder
Inputs
a
high
signal
when
de-emphasis
is
on,
and
a
low
signal
when
de-emphasis
is
off.
SBSO
read
out
clock
input.
Connects
these
pins
to
photo
diodes
F
and
E.
F
I-
V
and
E
I-V
amplifier
inverted
input.
Focus
zero-cross
comparator
input.
Focus
actuator
Connects
the
capacitor
for
defect
time
constant.
Focus
error
signal
Focus
amplifier
inverted
input.
Focus
drive
output.
Focus
servo
bias
Feed
motor
Focus
error
input.
,
Focus
error
amplifier
output.
Connected
internally
to
the
window
comparator
input
for
bias
adjust-
ment;
Focus
servo
bias
Fast
forward
tracking
control
Ground
this
pin
through
a
capacitor
for
cutting
the
focus
servo
high-frequency
gain.
Master
PLL
filter
input.
Master
PLL
(slave-digital
PLL)
filter
output.
External
time
constant
setting
pin
for
boosting
the
focus
servo
low-frequency.
Focus
actuator
O/P
Focus
OK
comparator
output.
Focus
OK
input.
Used
for
SENS
output
and
the
servo
auto
sequencer.
Fast
rewind
tracking
control
Peak
frequency
setting
pin
for
focus
and
tracking
phase
compensator
amplifier.
Focus
search
GFS
output.
GTPO
output.
Connects
the
external
capacitor
to
set
the
current
which
determines
the
Focus
Track.
servo
front
jump
Track.
servo
rear
jump
APC
amplifier
output.
Laser
diode
on
Comparator
input
for
balance
adjusement.
(input
from
TEO
through
LPF)
D/A
interface.
LRclock
output
f
=
fs.
LR
clock
input.
Spindle
motor
servo
control.
Spindle
motor
servo
control.
Mirror
detection
MNTO
output.
MNT1
output.
MNT3
output.
Spindie
motor
on/off
contro!
output.
MUT
MUTG
OTD
PCMD
PCMDI
PCO
PD
PD1
PD2
PORE
RA
RAB
RDO
RF
RF-!
RF-M
RF-O
point.
RFCK
RFTC
control.
SBSO
SCOR
SEG3
SEIN
SENS1
SENS2
SICL
SIDA
SILD
SL
SL-M
SL-O
SL-P
SLED
SLEND
SLIN
SLOUT
SPDL
SQCK
SRCH
SUBQ
TA
TA-M
TA-O
TDFCT
TE
TEO
TG2
TGU
TRAY
TZC
V16M
PLL.
V4
VCKI
VCTL
PLE:
Vee
WFCK
XLT
XLTO
XPCK
XROF
XRST
XRST
XRSTO
XTAI
AF.Muting
Muting
Off
track
detector
D/A
interface.
Serial
data
output
(two’s
comple-
ment,
MSB
first).
D/A
interface.
Serial
data
intput
(two’s
complement,
MSB
first).
Master
PLL
charge
pump
output.
APC
amplifier
input.
RF
I-V
amplifier
inverted
input.
Connect
these
pins
to
the
photo
diode
A+
C
and
B
+
D
pins.
RF
I-V
amplifier
inverted
input.
Connect
these
pins
to
the
photo
diode
A+
C
and
B+
D
pins.
Power
on
reset
enable
input
Radial
actuator
O/P
Interface
R/W
and
aknoledge
input
Radial
detector
signal
EFM
signal
input.
Input
for
the
RF
summing
amplifier
output
with
capacitance
coupled.
RF
summing
amplifier
inverted
input.
the
RF
ampli-
fier
gain
is
determined
by
the
resistance
connected
between
the
pin
and
RFO
pin.
RF
summing
amplifier
output.
Eyepattern
check
RFCK
output.
External
time
constant
setting
pin
during
RF
level
Sub
P
to
W
serial
output.
Output
a
high
signal
when
either
subcode
sync
SO
or
S1
is
detected.
Sef
3
output
for
LED.
SENS
input
from
SGP
Outputs
FZC,
DFCT1,
TZC,
BALH,
TGH, FOH,
ATSC,
and
others
according
to
the
CPU.
Outputs
DFCT2,
MIRR,
BALL,
TGL,
FOL,
and
others
according
to
the
command
from
the
CPU.
Serial
interface
clock
Serial
interface
data
Serial
interface
load
Sledge
O/P
Sled
amplifier
inverted
input.
Sled
drive
output.
Sled
amplifier
non-inverted
input.
Sled
motor
End
of
slider
stroke
signal
Slider
closing
control
Slider
opening
control
Spindle
motor
Subcode
Q
clock
External
time
constant
setting
pin
for
generating
focus
search
waveform.
Subcode
Q
Tracking
actuator
Tracking
amplifier
inverted
input.
Tracking
drive
output.
Connects
the
capacitor
for
defect
time
constant.
Tracking
error
signal
Tracking
error
amplifier
output.E-F
signal
is
output.
External
time
constant
setting
pin
for
switching
trac-
king
high-frequency
gain.
External
time
constant
setting
pin
for
switching
trac-
king
high-frequency
gain.
Tracking
motor
Tray
motor
Tracking
zero-cross
comparator.
VCO2
oscillation
output
for
the
wide-band
EFM
Versatile
O/P
pin
VCO2
oscillation
input
for
the
wide-band
EFM
PLL.
VCO2
control
voltage
input
for
the
wide-band
EFM
Negative
power
supply.
WFCK
output.
Latch
input
from
CPU.
(no
pull-up
resistance)
Serial
data
latch
output
XPLCK
output.
XRAOF
output.
Reset
input;
resets
at
Low.
(no
pull-up
resistance)
System
reset.
Reset
output.
Crystal
oscillation
input.
Input
the
external
master
clock
via
this
pin.

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