7-7
(25) Pin 25 is a terminal for ver blanking output.
The output voltage is approx. 5V when the terminal is set in
high impedance.
HIGH period of output is independent of frequency of ver
sync signal which is input at pin 30. This terminal rises at
front edge of ver sync signal, and the rising is delayed by
approx. 100 µs from the rising of pin24.
(27) Pin 27 is a terminal which is connected with capacitor
which produces RAMP wave output at pins 25 and 26.
Recommended value is 0.015 µF, and if this value of capacitor
is increased, respective absolute or maximum values of
Tvshift, Tvd (pin 24 output), and Tvd-vblk (pin 25 output)
can be enlarged, keeping the conditions below.
2K
0.5V
100
68K
25
Fig. 22
(26) Pin 26 is V SHIFT terminal.
The control voltage range is 0 to 2.5V. When this terminal
voltage is 0V, ver output of pin 24 rises at the same time as
ver sync signal. By controlling this terminal voltage up to
2.5V, ver output of pin 24 can be delayed up to 470 µs from
the front porch of ver sync signal.
73U
100
27
0.015 F
Fig. 24
26
36K
Fig. 23
24
Tvshift
Tvd
Tvd-vblk
Tshift : Tvd : Tvd-vblk = 470 : 300 : 100
PIN VDRIVE
PIN VBLK
V.SYNC
25
Fig. 25
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