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Trio CS-1575 - VERTICAL AMPLIFIER CIRCUIT; SYNC SWEEP CIRCUIT

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CIRCUIT
DESCRIPTION
VERTICAL
AMPLIFIER
CIRCUIT
Note:
Parts
symbols
in
(
)
are
for
CH2.
The
vertical
amplifier
circuit
has
two
identical
preamplifiers
for
CH1
and
CH2.
A
signal
applied
to
the
BNC
INPUT
termina!
passes
through
the
AC-GND-DC
switch
and
is
fed
to
the
1st
attenuator
where
the
signal
is
attenuated
to
1/1,
1/10
or
1/100
so
as
to
be
inputted
to
the
gate
of
Q2
(Q12).
Q2
(Q12)
is
a
dual
FET
which
has
excellent
DC
balance
against
changes
in
temperatures
and
also
has
a
high
input
impedance.
Qi1
(Q11)
is
an
input
protection
circuit
utilizing
the
excellent
diode
characteristics
of
FET,
which
is
used
to
protect
Q2
(Q12)
from
excessive
input.
The
source
circuit
of
Q2
(Q12)
has
VR8
(VR18)
to
adjust
VARI.
ATT
and
DC.
BALANCE.
The
signal
from
Q2
(Q12)
is
fed
through
the
emitter
follower
Q3
and
Q4
(Q13
and
Q14)
to
the
2nd
attenuator
Q5
and
Q6
(Q15
and
Q16).
The
collector
of
Q5
and
Q6
(Q15
and
Q16)
forms
an
att-
enuator
to
attenuate
the
signal
to
1/1
or
1/3,
while
VR3
(VR13)
is
used
to
adjust
STEP
ATT
and
DC.
BALANCE.
VR2
{VR12)
in
the
emitter
circuit
of
these
transistors
is
used
to
adjust
the
gain
(VARIABLE
ATT).
The
gain
is
calibrated
by
VR1
(VR11).
The
signal
from
the
2nd
attenuator
is
fed
to
the
preamplifier
Q7
and
Q8
(Q17
and
Q18).
VR5
(VR15)
in
the
emitter
circuit
of
these
transistors
is
the
&
POSITION
control
and
VR4
(VR14)
is
the
ADJUST
control.
VRQ
(VR19)
is
used
to
calibrate
the
gain
at
X1O0MAG.
The
signal
from
the
preamplifier
is
fed
to
the
“V"
mode
logic
circuit
consisting
of
diode
gate
(D3
~
10)
inserted
to
the
cascode
amplifier
Q9
(Q19),
Q10
(Q20),
Q21
and
Q22
and
the
cascode
junction,
in
which
the
signal
is
switched
to
a
dual
trace
signal
and
is
fed
to
the
“V’
main
amplifier
O25
~
28
through
the
drive
amplifier
Q23
and
Q24
where
the
cent-
er
position
of
CRT
is
adjusted
by
VR6
inserted
in
the
emitter
circuit
of
Q25
and
Q26
to
prevent
the
dynamic
range
of
the
output
of
Q21
and
Q22
from
being
biased.
The
signal
from
the
preamplifier
is
sampled
and
is
fed
through
Q9
and
Q10
(Q19
and
Q20)
to
the
trigger
amplifier
Q29
and
Q30
(031
and
Q32),
which
is
further
fed
to
sync
circuit.
The
gain
of
the
“X”
amplifier
is
calibrated
by
VR17
while
the
X-POSITION
is
adjusted
by
VR16.
The
signal
is
then
amplified
through
the
‘’V”
main
amplifier
to
provide
sufficient
bandwidth
so
as
to
be
applied
to
the
vertic-
al
deflection
plate
of
CRT.
SYNC
SWEEP
CIRCUIT
The
signal
from
the
vertical
preamplifier
is
fed
through
the
trigger
amplifier
to
the
limiter
circuit
Q2
and
Q3
(04
and
Q5)
where
the
trigger
level
is
adjusted
by
VR1
(VR106).
The
CH2
limiter
circuit
04
and
O85
also
functions
as
a
limiter
circuit
for
external
triggering:
an
external
trigger
signal
which
passes
through
the
external
trigger
amplifier
Q21
and
a
CH2
trigger
signal
are
selected
by
the
trigger
source
switch
and
is
applied
te
the
base
of
Q5.
The
trigger
signal
from
the
limiter
circuit
is
shaped
to
square
wave
signal
through
the
Schmidt
circuit
“A”
(A’)
IC2a
and
b
(IC2c
and
d)
and
is
fed
to
the
mono
multi-circuit
|C3a
and
b
(IC3c
and
d).
The
mono
multi-circuit
is
controlled
through
Q6
(Q7)
by
the
auto-free-run
circuit
D3
and
D4
(D5
and
D6)
which
DC-
restores
the
output
of
the
Schmidt
circuit
““A’’
(A’),
and
the
trigger
mode
logic
circuit
|C1a,
b
and
d,
to
produce
negative
-
pulses
of
about
40
nsec
only
at
the
falling
time
of
the
output
of
the
Schmidt
circuit
“A”
(A’).
These
pulses
are
attenuated
to
1/2
by
R27
and
R33.
Since
the
negative
pulse
is
in
the
middle
of
the
threshold
level
of
the
Schmidt
circuit
““B”
IC4c
and
d,
it
inverts
the
output
of
this
circuit
from
‘‘H
(1)
to
“O”.
The
circuits
IC4a-d,
Q8-11
and
D13-16
form
one
loop
to
constitute
a
saw-tooth
wave
generating
circuit.
At
first,
the
output
of
the
Schmidt
circuit
‘B”
is
‘’H
(or
1)’,
so
D14
~
16
are
ON
and,
hence,
the
output
of
the
mirror
integ-
ration
circuit
is
almost
OV.
This
voltage
is
fed
through
the
emitter
follower
Q8
and
Q9Q
to
the
Schmidt
circuit
“C"
IC4a
and
b,
the
output
of
which
becomes
“’L
(0)
and,
therefore,
D13
is
set
to
“ON”.
lf,
at
this
time,
a
negative
pulse
is
fed
by
the
mono
multic-
ircuit,
the
output
of
the
Schmidt
circuit
“B’
becomes
‘‘L
(o)’
which
turns
D14
~
16
to
OFF
and
thus
the
time
base
capac-
itor
C21.
starts
charging
through
the
mirror
integration
circuit.
The
charge
current
is
determined
by
the
voltage
set
by
VR5
(SWP.
VARI)
and
VR3
(SWP.
TIME
ADJ.)
while
R44,
73,
45
and
46
are
selected
by
the
SWP.
TIME/DIV
switch
and
SWP.
TIME
SELECT
switch;
the
charge
current
is
applied
through
the
emitter
follower
O22,
The
charge
voltage
from
the
integration
circuit
is
fed
to
the
Schmidt
circuit
“C”
via
VR103
(SWP.
LENGTH),
Q8
and
Q9
and
when
it
reaches
the
threshold
level,
then
the
Schmidt
circuit
““B”
is
driven
where
the
output
is
inverted
from
‘’L
(O)”
to
“H
(1)
and
at
the
same
time
D13
is
turned
to
OFF.
When
the
output
of
the
Schmidt
circuit
becomes
H
(1),
D15
and
D16
turn
to
ON
and
the
integration
circuit
is
discharged
quickly
until
D14
turns
to
ON.
Also,
the
voltage
charged
in
the
hold-off
capacitor
C18
through
Q8
is
discharged
slowly
through
R42
because
D13
is
OFF;
this
voltage
is
fed
through
O89
to
the
Schmidt
circuit
“C”
where
the
output
is
inverted
and
D13
turns
to
ON,
thereby
returning
to
the
original
condition.

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