NINA-W1 series - System Integration Manual
UBX-17005730 - R07 System description Page 10 of 47
It is recommended to make the UART0 available either as test points or connected to a header for
firmware upgrade. The IO level of the UART will follow the VCC_IO.
1.7.2 Ethernet (RMII+SMI)
For NINA-W13, RMII is supported from software version 2.0.0 onwards.
For NINA-W15, direct MAC to MAC connection will be supported when the module reaches
Engineering Sample status.
The NINA-W1 series module includes a full RMII for Ethernet MAC to PHY communication using the
included Station Management Interface (SMI). The RMII and SMI use 9 signals in total. The interface
requires an external 50 MHz clock source either from a compatible PHY chip or from an external
oscillator. The NINA-W1 series module cannot provide this clock signal by itself.
The two-wire SMI is used to configure the PHY chip. It uses a clock line and a data line to setup the
internal registers on PHY chip.
Due to pin muxing of the RMII interface, there is a limitation in the functionality of NINA-W13/W15
series module when using RMII. The following functions will be turned off when RMII communication
is initiated:
• Red, Green and Blue LED will be disabled
• UART will be run without flow control as CTS and RTS functionality will be disabled
• DSR and DTR functionality will be disabled
A pull up resistor of 1.5 kΩ must be added to MDIO pin.
1.7.2.1 Startup precautions
The RMII_CLK input (GPIO27) is muxed with the boot pin and must be held high 1.2 ms after the
reset signal is released to ensure not to enter the boot mode.
EVK-NINA-W1 uses two buffers and a low pass filter to delay the reset signal going to the PHY
circuit. See Figure 4.
This will delay the clock so that it starts a short time after the module is released from reset.
Figure 4: Delay circuit for RMII clock
Also the u-blox connectivity software will sense the RMII_CLK input (GPIO27) at startup. If an RMII
clock is discovered, then Ethernet communication will be initiated.
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