NINA-W1 series - System Integration Manual
UBX-17005730 - R07 System description Page 7 of 47
Figure 3: Block diagram of NINA-W10 series
1.3 CPU
The NINA-W1 series has a dual-core system with two Harvard Architecture Xtensa LX6 CPUs with
maximum 240 MHz internal clock frequency. The internal memory of NINA-W1 includes the
following:
• 448 Kbyte ROM for booting and core functions
• 520 Kbyte SRAM for data and instruction
• 16 Mbit FLASH for code storage including hardware encryption to protect programs and data
• 1 kbit EFUSE (non- erasable memory) for MAC addresses, module configuration, Flash-
Encryption, and Chip-ID
The open CPU variants (NINA-W101/NINA-W102) also support external FLASH and SRAM memory
via a Quad SPI interface (see section 2.7.2.4).
1.4 Operating modes
1.4.1 Power modes
The NINA-W1 series modules are power efficient devices capable of operating in different power
saving modes and configurations. Different sections of the module can be powered off when not
needed and complex wake up events can be generated from different external and internal inputs.
For the lowest current consumption modes, an external LPO clock is required (available for NINA-
W10 series modules).
Flash (16Mbit)
Linear voltage regulators
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