Xilinx System Generator V2.1 - Parallel to Serial

Basic Elements 39
Xilinx Blocks
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Parallel to Serial
The Parallel to Serial block takes an input word and splits it into N time
multiplexed output words where N equals the number of input bits/
number of output bits. The order of the output is either least significant
bit first or most significant bit first.
The following waveform illustrates the block’s behavior:
Figure 3-14: Example of Parallel to Serial behavior
This example illustrates the case where the input width is 4, output width is 2, word
size is 1 bit, and the block is configured to output the least significant partial word
first.
Block Interface
The Parallel to Serial block has one input and one output port. The input port can be
any size. The output port size is indicated on the block parameters dialog box.