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General| Protocol | 1000BASE-X |
|---|---|
| Data Rate | 1 Gbps |
| Target Device | Xilinx FPGAs |
| Supported Standards | IEEE 802.3 |
| Implementation | Soft IP |
| Product Name | LogiCORE IP 1000BASE-X |
| Core Type | Soft IP |
| Interface | GMII, RGMII, SGMII, TBI |
Provides information about generating, customizing, and simulating the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII core.
Outlines the structure and content of the user guide, detailing each chapter's scope and topic.
Describes the Ethernet 1000BASE-X PCS/PMA or SGMII core as a Xilinx CORE Generator IP.
Lists additional documents available for the core, including data sheets, release notes, and user guides.
Explains how to obtain technical support from Xilinx for the core and its usage guidelines.
Introduces the core's function in implementing PCS/PMA sub-layers or as a GMII to SGMII bridge with RocketIO transceivers.
Explains the client-side GMII interface, usable internally or externally via device IOBs.
Details the optional MDIO interface signals for accessing PCS Management Registers, connected to MAC devices.
Discusses core ports as internal FPGA fabric connections and the role of the HDL example design.
Introduces the GUI screen used for setting core parameters and options during generation.
Describes the options for selecting the core's operational standard: 1000BASE-X, SGMII, or Both.
Details the two physical interface options: RocketIO transceiver and Ten Bit Interface (TBI).
Lists the files output by CORE Generator, including netlists, HDL example designs, and scripts.
Introduces creating designs using the core, based on the delivered example design implementations.
Illustrates the example design for 1000BASE-X mode with RocketIO transceivers, split into block and top levels.
Provides guidance for creating designs using the core, emphasizing adherence to provided steps for success.
Provides guidelines for using the client-side GMII with the 1000BASE-X standard, referencing IEEE 802.3 for GMII definition.
Introduces figures illustrating GMII reception, noting clock signal source variation based on core options.
Details enabling the RocketIO transceiver's CRC functionality for Virtex-II Pro, with a caution for SGMII standard.
Describes external GMII receiver logic, showing registered output signals in IOBs and clock forwarding.
Explains the Ten-Bit Interface (TBI) logic, split into hierarchical layers for customer design instantiation.
Introduces receiver logic for TBI, detailing signal names and logic matching example designs.
Illustrates sharing clock resources across multiple core instances using TBI, emphasizing gtx_clk sharing.
Describes the logic for interfacing the core with RocketIO transceivers across supported device families.
Details core integration with Virtex-II Pro RocketIO MGT, connections, logic, and constraints for 1000BASE-X.
Illustrates clock sharing for multiple core instances with Virtex-II Pro MGTs, emphasizing shared userclk, userclk2, and brefclk.
Introduces two Rx Elastic Buffer implementations: RocketIO transceiver buffer and FPGA fabric buffer.
Explains that system connections and clock circuitry are identical to 1000BASE-X when using RocketIO Rx Elastic Buffer.
Illustrates clock sharing for multiple core instances with fabric Rx Elastic Buffer and Virtex-II Pro MGTs, including area constraints.
Explains accessing core configuration and status via Management Registers through the MDIO interface.
Details the Control Register (Register 0) for 1000BASE-X, explaining bits like Reset, Loopback, and Speed Selection.
Describes the Status Register (Register 1) for 1000BASE-X, covering bits for link status and auto-negotiation.
Explains SGMII registers adapted from IEEE 802.3, covering SGMII link and Medium states.
Explains Auto-Negotiation requirements: must be enabled or disabled in both devices for proper function.
Describes the 1000BASE-X Auto-Negotiation function as per IEEE 802.3 clause 37, enabling advertisement of supported modes.
Illustrates SGMII Auto-Negotiation operation, highlighting PHY's two sides and core's reliance on PHY results.
Explains the an_interrupt port for signaling Auto-Negotiation completion, controlled via MDIO Register 16.
Illustrates a typical application scenario for dynamic switching between 1000BASE-X and SGMII standards using an external PHY.
Explains selecting the default standard (1000BASE-X or SGMII) via the basex_or_sgmii port or MDIO.
Details switching the core's standard (1000BASE-X/SGMII) using MDIO Register 17 and subsequent register interpretation.
Outlines constraints for implementing the core, including device selection and IOB requirements.
Details constraints for Virtex-II Pro MGTs in 1000BASE-X, referencing example UCF sections and HDL source code.
Illustrates and specifies setup and hold time windows for TBI input signals, defining the worst-case data valid window.
Discusses integrating the core with the 1-Gigabit Ethernet MAC core for extended system functionality.
Explains providing SGMII functionality by integrating core with 1-Gigabit MAC, noting Rx Elastic Buffer usage and optional SGMII Adaptation Module.
Discusses integrating the core with the Tri-Mode Ethernet MAC core for MAC sublayer functionality at multiple speeds.
Discusses power management for the core, particularly with RocketIO transceivers, using PCS Configuration Register 0 or configuration_vector.
Details startup sequencing, emphasizing the need to exit the isolate state via PCS Configuration Register 0 or configuration_vector.
Explains loopback mode implementation, enabled/disabled via MDIO or Optional Configuration Vector.
Describes using a functional model generated by CORE Generator for simulation during the design phase.
Details the synthesis process using XST for VHDL designs, including creating XST project and script files.
Introduces the implementation phase, starting with generating the Xilinx netlist using ngdbuild.
States the core has been verified through extensive simulation and hardware verification.
Describes using a parameterizable transaction-based test bench for simulation, covering register access, sync loss, and frame handling.
Details hardware verification on test platforms, including 1000BASE-X with 1-Gigabit MAC and SGMII with Tri-speed MAC.
Provides latency measurements for the core only (excluding IOBs/Elastic Buffer) for 1000BASE-X PCS with TBI.
Provides core-only latency measurements for 1000BASE-X PCS/PMA with RocketIO transceiver.
Explains DCM usage for input setup/hold requirements with TBI/GMII, involving static alignment via phase shift.
Recommends extensive hardware integration investigation for phase shift settings, as empirical recommendations are not provided.
Illustrates GMII encoding translation to code-group stream by PCS Transmit Engine for even transmission case.
Illustrates reception of inbound code-group stream for even case, translating to receiver GMII via PCS Receive Engine.
Illustrates reception of inbound code-group stream for odd case, translating to receiver GMII via PCS Receive Engine, noting preamble byte loss.
Illustrates RocketIO transceiver Rx Elastic Buffer depths and thresholds, and translates buffer sizes to maximum frame sizes.
Illustrates FPGA fabric Rx Elastic Buffer depth and thresholds for SGMII, discussing its optional use and buffer analysis.
Describes TBI Rx Elastic Buffer for SGMII/Dynamic Switching and 1000BASE-X, noting its smaller size for logic saving and low latency.
Lists general checks for debugging, including timing constraints, clock sources, and DCM lock status.
Guides on debugging MDIO issues, checking MDIO drive, mdc clock, register reads, and PHYAD field.
Addresses issues with data reception/transmission, focusing on link establishment, Auto-Negotiation status, and Isolate state.
Provides steps to determine Auto-Negotiation completion success and troubleshoot if it's not completing, including checking bit errors.
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