Xilinx LogiCORE 1000BASE-X - Figure 7-6: Clock Management - Multiple Core Instances, Mgts for 1000 Base-X

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 89
UG155 March 24, 2008
Clock Sharing Across Multiple Cores with RocketIO
R
Figure 7-6: Clock Management - Multiple Core Instances, MGTs for 1000BASE-X
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
IPAD
brefclkp
(250MHz)
IPAD
brefclkn
(250MHz)
Virtex-4
GT11CLK_MGT
MGTCLKP
MGTCLKN
SYNCLK1OUT
Virtex-4
GT11
RocketIO
(A)
REFCLK1
MGT tile
Virtex-4
GT11
RocketIO
(B)
REFCLK1
TXOUTCLK1
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
NC
userclk2
(125 MHz)
BUFG
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
synclk1
(250MHz)
‘0’
‘0’
‘0’
‘0’
TXOUTCLK1
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Virtex-4
GT11
RocketIO
(A)
REFCLK1
MGT tile
Virtex-4
GT11
RocketIO
(B)
REFCLK1
TXOUTCLK1
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
NC
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
‘0’
‘0’
‘0’
‘0’
TXOUTCLK1
component_name_block
(Block Level)
NC