Xilinx LogiCORE 1000BASE-X - Figure 8-4: Sgmii Connection to a Virtex-4 Mgt

102 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
R
Caution! The PHY connected via SGMII may always provide dynamic SGMII data (when
powered up). If not, and if signal_detect is not present, the RX_SIGNAL_DETECT port of the
calibration block must be driven by an alternative method. See XAPP732 for more information.
Figure 8-4: SGMII Connection to a Virtex-4 MGT
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
Virtex-4
GT11
RocketIO
(used)
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
userclk
userclk2
IPAD
IPAD
brefclkn
(250 MHz)
rxbufstatus[1:0]
rxchariscomma
rxcharisk
rxclkcorcnt[2:0]
rxdata[7:0]
rxrundisp
powerdown
txchardispmode
txchardispval
txcharisk
txdata[7:0]
enablealign
RXCHARISCOMMA[1:0]
RXCHARISK[1:0]
RXDATA[15:0]
RXRUNDISP[1:0]
POWERDOWN
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
TXDATA[7:0]
ENPCOMMAALIGN
ENMCOMMAALIGN
Virtex-4
GT11CLK_MGT
MGTCLKP
MGTCLKN
SYNCLK1OUT
RXDISPERR[1:0]
rxdisperr
brefclkp
(250 MHz)
REFCLK1
synclk1
'0'
TXOUTCLK1
FPGA
fabric
Rx
Elastic
Buffer
RXNOTINTABLE[1:0]
rxnotintable
BUFR
RXRECCLK1
'0'
userclk2 (125MHz)
BUFG
component_name_block
(Block Level from
example design)
Cal Block v1.4.1
DCLK
DCLK
TX_SIGNAL_DETECT
RX_SIGNAL_DETECT
'1'
signal_detect
dclk
BUFG